US4584561A
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Method of residue to analog conversion
Assignee: AG Communication Systems Corp
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Filing: 1984-09-24
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Granted: 1986-04-22
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Expires: 2004-09-24
Abstract
Abstract In a residue number system defined by the moduli set {p1=2 n -1, p2=2 n , p3=2 n +1}, a method of converting residue numbers {m1,m2,m3} to associated analog signals r(m1,m2,m3) comprises the steps of selecting a first binary signal satisfying the relationships |m1*S3+m3*S1| p1*p3 (where the constant S1=p1*p2/2 and S3=p2*p3/2) from a first look-up table; and summing the n less significant bits of this first digital signal and the negative of the residue digit signal m2 in a first binary adder for generating a second binary signal that is representative of the difference therebetween, taken modulo p2. This second binary signal addresses a second look-up table containing third binary signals which correspond to possible values of the product of the second binary signal and p1 and p3. Selected first and third binary signals are summed in a second binary adder for producing a binary output signal r(m1,m2,m3) that is representative of the residue number {m1,m2,m3}. This binary output signal is converted to a corresponding analog signal in a standard D/A converter. In an alternate method, 2n binary 0's are stuffed as less significant bits of the second binary signal prior to subtracting the latter from this bit shifted signal for producing the third binary signal. In yet another method, the first binary signal is obtained by selecting the binary signals m1*S3 and m3*S1 from associated look-up tables prior to summing them modulo p1*p3.
Inventors
- 👤 Peter S. Bernardson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:48
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/14; H03M7/18
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
165 words
The method of converting a binary representation of a residue signal {m1,m2,m3} in a prescribed residue number system that is defined by the moduli set {p1=2 n -1, p2=2 n , p3=2 n +1}, where n is an integer, to an associated binary output signal r(m1,m2,m3), said method comprising the steps of: first producing a first digital signal that is a binary representation of the sum of the product terms m1*S3 and m3*S1, the sum being taken modulo p1*p3, where S1=(p1*p2)/2 and S3=(p2*p3)/2; second producing a second signal that is a binary representation of the difference between binary bits of the first signal and the binary representation of the residue signal m2, the difference between taken modulo p2; third producing a third signal that is a binary signal representation of the product of the second signal and the constants p1 and p3; and first summing the first and third signals for producing the binary output signal r(m1,m2,m3) that is associated with the residue signal {m1,m2,m3}.
Claim 2
Independent Claim
165 words
The method of converting a binary representation of a residue signal {m1,m2,m3} in a prescribed residue number system that is defined by the moduli set {p1=2 n -1, p2=2 n , p3=2 n +1}, where n is an integer, to an associated binary output signal r(m1,m2,m3), said method comprising the steps of: first producing a first digital signal that is a binary representation of the sum of the product terms m1*S3 and m3*S1, the sum being taken modulo p1*p3, where S1=(p1*p2)/2 and S3=(p2*p3)/2; second producing a second signal that is a binary representation of the difference between binary bits of the first signal and the binary representation of the residue signal m2, the difference between taken modulo p2; third producing a third signal that is a binary signal representation of the product of the second signal and the constants p1 and p3; and first summing the first and third signals for producing the binary output signal r(m1,m2,m3) that is associated with the residue signal {m1,m2,m3}.
Claim 3
Dependent Claim
19 words
The method according to claim 1 wherein said first summing step is accomplished with a first binary adder circuit.
Claim 4
Dependent Claim
29 words
The method according to claim 2 wherein said second producing step takes into consideration the n less significant bits of the first signal, which is the modulo p1*p3 signal.
Claim 5
Dependent Claim
28 words
The method according to claim 3 wherein said second producing step is accomplished with a second binary adder circuit which operates as a modulo 2 n modulo adder.
Claim 6
Dependent Claim
67 words
The method according to claim 4 wherein said third producing step comprises the steps of: storing a look-up table of values of the products of p1, p3 and possible values of the second signal in associated memory locations of a first memory device; addressing a prescribed memory location of the first memory device with the second signal; and outputting the third signal from the addressed memory location.
Claim 7
Dependent Claim
62 words
The method according to claim 4 wherein said third producing step comprises the steps of: inserting 2n binary 0's as the less significant bits ahead of bits in the second signal for producing a bit shifted signal; and second summing the bit shifted signal and the negative of the second signal for producing a difference signal which corresponds to the third signal.
Claim 8
Dependent Claim
18 words
Apparatus according to claim 6 wherein said second summing step is accomplished with a third binary adder circuit.
Claim 9
Dependent Claim
74 words
Apparatus according to claim 4 wherein said first producing step comprises the steps of: storing a look-up table of modulo p1*p3 sums of the possible values of the m1*S3 and M3*S1 product terms in associated memory locations of a first memory device; addressing a prescribed memory location of the first memory device with the residue signals m1 and m3; and outputting the first signal from the addressed memory location of the first memory device.
Claim 10
Dependent Claim
85 words
The method according to claim 4 wherein said first producing step comprises the steps of: storing first and second look-up tables of the products m1*S3 and m3*S1 in associated memory locations of associated first and second memory devices; addressing prescribed memory locations of the first and second look-up tables with associated residue signals m1 and m3; outputting the prescribed signals from the prescribed memory locations; and third summing the two each outputted-prescribed product signals modulo p1*p3 for generating a signal corresponding to the first signal.
Claim 11
Dependent Claim
67 words
The method according to claim 8 wherein said third producing step comprises the steps of: storing a look-up table of values of the products of p1, p3 and possible values of the second signal in associated memory locations of a second memory device; addressing a prescribed memory location of the second memory device with the second signal; and outputting the third signal from the addressed memory location.
Claim 12
Dependent Claim
62 words
The method according to claim 9 wherein said third producing step comprises the steps of: inserting 2n binary 0's as the less significant bits ahead of bits in the second signal for producing a bit shifted signal; and second summing the bit shifted signal and the negative of the second signal for producing a difference signal which corresponds to the third signal.
Claim 13
Dependent Claim
17 words
The method according to claim 11 wherein said second summing step is accomplished with a binary adder.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-21 | 1989-10-21 | 1990-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-21 | 1993-10-21 | 1994-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-21 | 1997-10-21 | 1998-04-22 | $7700.00 | Window Closed / Lapsed |