US4584562A
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Method of residue to analog conversion
Assignee: AG Communication Systems Corp
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Filing: 1984-09-24
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Granted: 1986-04-22
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Expires: 2004-09-24
Abstract
Abstract A method is disclosed for accomplishing modulo 2 2n -1 addition with apparatus requiring adders that may be all standard binary adders. The method requires summing binary input signals a and b to produce a first sum signal in which the n+2 more significant bits thereof represent the integer part of a+b taken modulo 2 2n . These n+2 more significant binary bits are subtracted from a 2n bit shifted product representation thereof for producing a first difference signal. This difference signal is subtracted from the first sum signal to produce a binary signal R. When R is greater than or equal to the constant (2 2n -1), this constant is subtracted from the signal R for producing a binary signal that is the first sum signal a+b taken modulo 2 2n -1 .
Inventors
- 👤 Peter S. Bernardson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 09:27
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/14; H03M7/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
232 words
The method of converting binary signals a and b, which are made up of pluralities of binary bits, to a binary representation of the sum thereof taken modulo p1*p3, comprising the steps of: summing the signals a and b for producing a first binary signal; operating on bits of the first signal for producing a second binary signal which is proportional to the product of the constant 2 2n and the integer part of the first signal divided by 2 2n ; first combining the second signal and said bits of the first signal for producing a third binary signal which is proportional to the difference between the second signal and the integer part of the first signal divided by 2 2n ; second combining the first signal and the third signal for producing a fourth binary signal that is proportional to the difference therebetween; first generating a fifth binary signal that is proportional to a constant (2 2n -1); first comparing the fourth signal with the fifth signal and passing the fifth signal as a sixth binary signal only when the fourth signal is greater than or equal to said constant (2 2n -1); and third combining the fourth signal and the sixth signal for producing a seventh binary signal which is proportional to the difference therebetween and which corresponds to the desired output signal a+b taken modulo (2 2n -1).
Claim 2
Independent Claim
232 words
The method of converting binary signals a and b, which are made up of pluralities of binary bits, to a binary representation of the sum thereof taken modulo p1*p3, comprising the steps of: summing the signals a and b for producing a first binary signal; operating on bits of the first signal for producing a second binary signal which is proportional to the product of the constant 2 2n and the integer part of the first signal divided by 2 2n ; first combining the second signal and said bits of the first signal for producing a third binary signal which is proportional to the difference between the second signal and the integer part of the first signal divided by 2 2n ; second combining the first signal and the third signal for producing a fourth binary signal that is proportional to the difference therebetween; first generating a fifth binary signal that is proportional to a constant (2 2n -1); first comparing the fourth signal with the fifth signal and passing the fifth signal as a sixth binary signal only when the fourth signal is greater than or equal to said constant (2 2n -1); and third combining the fourth signal and the sixth signal for producing a seventh binary signal which is proportional to the difference therebetween and which corresponds to the desired output signal a+b taken modulo (2 2n -1).
Claim 3
Dependent Claim
17 words
The method according to claim 1 wherein said summing step is accomplished with a first binary adder.
Claim 4
Dependent Claim
18 words
The method according to claim 2 wherein said first combining step is accomplished with a second binary adder.
Claim 5
Dependent Claim
54 words
The method according to claim 3 wherein said bits of the first signal comprise a prescribed number of more significant bits of the first signal which correspond to the integer part of the first signal divided by 2 2n , and which are applied to a difference input terminal of the second binary adder.
Claim 6
Dependent Claim
63 words
The method according to claim 4 wherein said operating step comprises inserting 2n binary 0's as less significant bits ahead of said prescribed number of more significant bits of the first signal to produce the second signal that is a bit shifted signal that corresponds to a product signal and which is applied to a sum input terminal of the second binary adder.
Claim 7
Dependent Claim
18 words
The method according to claim 5 wherein said second combining step is accomplished with a third binary adder.
Claim 8
Dependent Claim
18 words
The method according to claim 6 wherein said third combining step is accomplished with a fourth binary adder.
Claim 9
Dependent Claim
17 words
The method according to claim 7 wherein said first comparing step comprises second and third comparing steps.
Claim 10
Dependent Claim
17 words
The method according to claim 3 wherein a and b comprise 3n+1 and 2n binary bits, respectively.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-21 | 1989-10-21 | 1990-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-21 | 1993-10-21 | 1994-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-21 | 1997-10-21 | 1998-04-22 | $7700.00 | Window Closed / Lapsed |