Abstract The memory matrix comprises parallel and alternating source and drain lines, floating gate areas placed between the source and drain lines and control gate lines parallel to each other and perpendicular to the source and drain lines superimposed on the floating gate areas. The floating gate areas are arranged in rows parallel to the source and drain lines in positions longitudinally staggered in relation to those of the adjacent row in such a manner that the floating gate areas of one row underlie a first plurality of control gate lines and the floating gate areas of the adjacent row underlie a second plurality alternating with the first of the control gate lines. The floating gate areas together with the adjacent source and drain lines and with the superimposed control gate lines define respective EPROM cells arranged in a staggered manner in the memory matrix.
Memory matrix with EPROM cells comprising parallel and alternating source and drain lines, floating gate areas placed between said source and drain lines and control gate lines parallel with each other and perpendicular to said source and drain lines superimposed on said floating gate areas, wherein said floating gate areas are arranged in rows parallel to said source and drain lines in positions longitudinally staggered in relation to those of an adjacent row in such a manner that the floating gate areas of a row underlie a first plurality of said control gate lines and the floating gate areas of the adjacent row underlie a second plurality of said control gate lines alternating with the first plurality of said control gate lines.
Claim 2
Dependent Claim
122 words
Memory matrix with EPROM cells comprising parallel and alternating source and drain lines, floating gate areas placed between said source and drain lines and control gate lines parallel with each other and perpendicular to said source and drain lines superimposed on said floating gate areas, wherein said floating gate areas are arranged in rows parallel to said source and drain lines in positions longitudinally staggered in relation to those of an adjacent row in such a manner that the floating gate areas of a row underlie a first plurality of said control gate lines and the floating gate areas of the adjacent row underlie a second plurality of said control gate lines alternating with the first plurality of said control gate lines.
Claim 3
Dependent Claim
68 words
Memory matrix in accordance with claim 1 wherein each floating gate area consists of a polysilicon strip which extends parallel to said source and drain lines from one field oxide area to the other placed between said source and drain lines, there being superimposed on said polysilicon strip a layer of dielectric oxide and over that a polysilicon strip forming a single body with a control gate line.