US4896295A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Eprom memory cell with two symmetrical half-cells and separate floating gates
Assignee: STMicroelectronics SRL
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Filing: 1988-03-14
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Granted: 1990-01-23
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Expires: 2008-03-14
Abstract
Abstract An EPROM memory cell including a source, a drain, a floating gate and a control gate with interposed dielectric oxide is made up of two symmetrical half-cells having the drain and the control gate in common, the sources physically separated but electrically connected with each other and the floating gates separated physically and electrically.
Inventors
- 👤 Giuseppe Corda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:35
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
138 words
An EPROM memory cell matrix comprising a silicon substrate; a plurality of parallel drain lines formed on said substrate; a plurality of parallel source lines formed on said substrate and alternating with said drain lines; floating gate areas spanning said drain lines and source lines; a plurality of parallel control gate lines arranged perpendicularly to said drain and source lines and superimposed on and self-aligned with said floating gate areas; and oxide areas electrically separating said drain lines, said source lines, said floating gate areas, and said control gate lines; wherein all of said source lines are electrically connected together so that each cell of said matrix comprises two symmetrical half-cells having a drain and a control gate in common, with respective sources being separated physically but connected electrically and respective floating gates being separated physically and electrically.
Claim 2
Dependent Claim
138 words
An EPROM memory cell matrix comprising a silicon substrate; a plurality of parallel drain lines formed on said substrate; a plurality of parallel source lines formed on said substrate and alternating with said drain lines; floating gate areas spanning said drain lines and source lines; a plurality of parallel control gate lines arranged perpendicularly to said drain and source lines and superimposed on and self-aligned with said floating gate areas; and oxide areas electrically separating said drain lines, said source lines, said floating gate areas, and said control gate lines; wherein all of said source lines are electrically connected together so that each cell of said matrix comprises two symmetrical half-cells having a drain and a control gate in common, with respective sources being separated physically but connected electrically and respective floating gates being separated physically and electrically.
Claim 3
Dependent Claim
25 words
The memory cell matrix in accordance with claim 1 wherein said source lines, drain lines, and control gate lines are equally spaced from each other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-22 | 1993-07-24 | 1994-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-22 | 1997-07-24 | 1998-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-22 | 2001-07-24 | 2002-01-23 | $7700.00 | Window Closed / Lapsed |