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Patent US5003566A successfully refreshed from Google Patents.
US5003566A
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Hyperfrequency circuit comprising a dynamic divide-by-two frequency divider circuit employing single interrupt FET, buffer and inverter in a loop
Assignee: US Philips Corp
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Filing: 1989-06-09
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Granted: 1991-03-26
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Expires: 2009-06-09
Abstract
Abstract A hyperfrequency dynamic divide-by-two frequency divider circuit includes an inverter stage A and a follower stage B, in which the output of the inverter stage is applied to the input of the follower stage via an interrupt transistor T 1 which is controlled by the hyperfrequency input signal H having a frequency f e . The output Q of the follower stage B is fed back to the input of the inverter stage A and supplies the output signal having a frequency f=f e /2. The operation of the divider takes place subject to the conditions: 1/[(α+1) Tpd]≦f.sub.e ≦1/[(α+1)τ.sub.1 ] where α=(T e -τ)/τ, in which relations τ 1 is the propagation time in the interrupt transistor, α is the duty cycle, T e is the period of the input signal, τ is the period during which the interrupt transistor T 1 is closed, and Tpd is the total propagation time which is formed by the sum of the propagation times in the inverter stage, the interrupter and the following stage.
Inventors
- 👤 Bertrand Gabillard
- 👤 Marc Rocchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:13
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0952; H03K5/00; H03K5/00006
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
73 words
An integrated semiconductor circuit, comprising a divide-by-two frequency divider circuit which comprises a loop which includes an inverter stage (A), a follower stage (B) and consisting solely of a single interrupt transistor channel (T 1 ) having a control input for an input signal (H) which is periodic at the frequency to be divided, the divider circuit utilizing aggregated propagation delays of the said inverter and follower stages and the single interrupt transistor.
Claim 2
Dependent Claim
73 words
An integrated semiconductor circuit, comprising a divide-by-two frequency divider circuit which comprises a loop which includes an inverter stage (A), a follower stage (B) and consisting solely of a single interrupt transistor channel (T 1 ) having a control input for an input signal (H) which is periodic at the frequency to be divided, the divider circuit utilizing aggregated propagation delays of the said inverter and follower stages and the single interrupt transistor.
Claim 3
Dependent Claim
22 words
A semiconductor circuit as claimed in claim 1, characterized in that the divider circuit is realized in Buffered FET Logic (BFL) technology.
Claim 4
Dependent Claim
37 words
An integrated semiconductor circuit as claimed in claim 1, characterized in that the divider circuit is realized in gallium arsenide using Buffered FET Logic (BFL) technology and comprises transistors of the MESFET or Heterostructure FET (HFET) type.
Claim 5
Dependent Claim
160 words
An integrated semiconductor circuit as claimed in claim 1, characterized in that the inverter stage (A) comprises an inverter transistor (T2), a source of which is connected to ground, a drain of which is connected to a first current source comprising, a supply voltage (V DD ) and a series load (R1), and a gate of which is coupled to an output of the follower stage (B), the inverter stage (A) also comprising a shifter stage which comprise a first shift transistor (T3), a gate of which is coupled to a first node common to the inverter transistor (T2) and the first current source, a drain of which is connected to the supply voltage (V DD ), and a source of which is connected to a second current source (T4, V SS ) via at least one diode (D1), a second node between the diode (D1) and the second current source constituting an output (Q) of the inverter stage (A).
Claim 6
Dependent Claim
79 words
An integrated semiconductor circuit as claimed in claim 1, characterized in that the follower stage (B) comprises a follower transistor (T5), a drain of which is connected to the supply voltage (V DD ), a source of which is connected to a third current source (T6, V SS ), the source of the follower transistor (T5) being an output of the follower stage (B) and a gate of which is connected to an output of the inverter stage (A).
Claim 7
Dependent Claim
31 words
An integrated semiconductor circuit as claimed in claim 4, characterized in that said second and third current sources comprise respective loads in series with a further supply voltage (V SS ).
Claim 8
Dependent Claim
79 words
An integrated semiconductor circuit as claimed in claim 4, characterized in that the follower stage (B) comprises a follower transistor (T5), a drain of which is connected to the supply voltage (V DD ), a source of which is connected to a third current source (T6, V SS ), the source of the follower transistor (T5) being an output of the follower stage (B), and a gate of which is connected to an output of the inverter stage (A).
Claim 9
Dependent Claim
31 words
An integrated semiconductor circuit as claimed in claim 5, characterized in that said second and third current sources comprise respective loads in series with a further supply voltage (V SS ).
Claim 10
Dependent Claim
31 words
An integrated semiconductor circuit as claimed in claim 7, characterized in that said second and third current sources comprise respective loads in series with a further supply voltage (V SS ).
Claim 11
Dependent Claim
22 words
A semiconductor circuit as claimed in claim 4, characterized in that the divider circuit is realized in Buffered FET Logic (BFL) technology.
Claim 12
Dependent Claim
22 words
A semiconductor circuit as claimed in claim 5, characterized in that the divider circuit is realized in Buffered FET logic (BFL) technology.
Claim 13
Dependent Claim
22 words
A semiconductor circuit as claimed in claim 6, characterized in that the divider circuit is realized in Buffered FET Logic (BFL) technology.
Claim 14
Dependent Claim
22 words
A semiconductor circuit as claimed in claim 9, characterized in that the divider circuit is realized in Buffered FET Logic (BFL) technology.
Claim 15
Dependent Claim
37 words
An integrated semiconductor circuit as claimed in claim 4, characterized in that the divider circuit is realized in gallium arsenide using Buffered FET Logic (BFL) technology and comprises transistors of the MESFET or Heterostructure FET (HFET) type.
Claim 16
Dependent Claim
37 words
An integrated semiconductor circuit as claimed in claim 5, characterized in that the divider circuit is realized in gallium arsenide using Buffered FET Logic (BFL) technology and comprises transistors of the MESFET or Heterostructure FET (HFET) type.
Claim 17
Dependent Claim
37 words
An integrated semiconductor circuit as claimed in claim 6, characterized in that the divider circuit is realized in gallium arsenide using Buffered FET Logic (BFL) technology and comprises transistors of the MESFET or Heterostructure FET (HFET) type.
Claim 18
Dependent Claim
37 words
An integrated semiconductor circuit as claimed in claim 9, characterized in that the divider circuit is realized in gallium arsenide using Buffered FET Logic (BFL) technology and comprises transistors of the MESFET or Heterostructure FET (HFET) type.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-25 | 1994-09-24 | 1995-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-25 | 1998-09-24 | 1999-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-25 | 2002-09-24 | 2003-03-26 | $7700.00 | Window Closed / Lapsed |