Patent US4460851A successfully refreshed from Google Patents.
Patent US5003310A successfully refreshed from Google Patents.
US5003310A
Expired / Lapsed
US
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Analog data acquisition circuit with digital logic control
Assignee: Sundstrand Corp
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Filing: 1989-09-29
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Granted: 1991-03-26
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Expires: 2009-09-29
Abstract
Abstract A data acquisition for use in a high-speed data bus interface is provided with an analog acquisition circuit having analog inputs, digital outputs, a load terminal, an end-of-conversion terminal, a strobe terminal, a multiplex address output and a channel select input. A static random access memory receives data produced at the digital output of the analog acquisition circuit and stores it in addresses corresponding to the multiplexed address outputs of the analog acquisition circuit. A simple logic control circuit having an AND gate, an OR gate and a one shot circuit is connected to control the operation of the analog acquisition to provide self-starting and free running operation with synchronous turn on and turn off to prevent data contamination when the circuit is stopped.
Inventors
- 👤 Roger D. Thornton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:43
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/05
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
177 words
A data acquisition circuit comprising: an analog acquisition circuit having a plurality of analog inputs, a plurality of digital outputs, an end-of-conversion terminal, a strobe terminal, and a multiplex address output; a random access memory having a plurality of inputs connected to the digital outputs of said analog acquisition circuit, a write terminal, an enable terminal, and an address input connected to the multiplex address output of said analog acquisition circuit; an AND logic gate having a first input for receiving an on/off control signal, a second input connected to said strobe output of said analog acquisition circuit, and an output; an OR logic gate having a first input connected to said end-of-conversion terminal of said analog acquisition circuit, a second input connected to the output of said AND gate, and an output connected to said strobe terminal of said analog acquisition circuit; and a one shot circuit having a first input connected to said strobe terminal of said analog acquisition circuit, and an output connected to said enable and write terminals of said random access memory.
Claim 2
Dependent Claim
177 words
A data acquisition circuit comprising: an analog acquisition circuit having a plurality of analog inputs, a plurality of digital outputs, an end-of-conversion terminal, a strobe terminal, and a multiplex address output; a random access memory having a plurality of inputs connected to the digital outputs of said analog acquisition circuit, a write terminal, an enable terminal, and an address input connected to the multiplex address output of said analog acquisition circuit; an AND logic gate having a first input for receiving an on/off control signal, a second input connected to said strobe output of said analog acquisition circuit, and an output; an OR logic gate having a first input connected to said end-of-conversion terminal of said analog acquisition circuit, a second input connected to the output of said AND gate, and an output connected to said strobe terminal of said analog acquisition circuit; and a one shot circuit having a first input connected to said strobe terminal of said analog acquisition circuit, and an output connected to said enable and write terminals of said random access memory.
Claim 3
Dependent Claim
154 words
A data acquisition circuit as recited in claim 1, wherein said one shot circuit comprises: a NOR circuit having a first input connected to said strobe terminal, an inverting input, and an output; a trigger circuit having an input and an output, said output being connected to said enable and write terminals of said static random access memory; a time delay circuit connected between said NOR circuit and said input of said trigger circuit; a second AND logic gate having a first input connected to the output of said trigger circuit, a second input, and an output connect to the inverting input of said NOR circuit; and a second OR logic gate having a first input connected to said strobe terminal of said analog acquisition circuit, a second input connected to the output of said second AND logic gate, and a an output connected to the second input of said second AND logic gate.
Claim 4
Dependent Claim
62 words
A data acquisition circuit as recited in claim 1, further comprising: a NAND logic gate having a plurality of inputs connected to the multiplex address output of said analog acquisition circuit and an output connected to a load terminal of said analog acquisition circuit; and means for supplying a preselected address signal to a channel select input of said analog acquisition circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-25 | 1994-09-24 | 1995-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-25 | 1998-09-24 | 1999-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-25 | 2002-09-24 | 2003-03-26 | $7700.00 | Window Closed / Lapsed |