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US4400801A
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Read/write circuit for a random access memory
Assignee: Hewlett Packard GmbH Germany
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Filing: 1980-12-04
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Granted: 1983-08-23
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Expires: 2000-12-04
Abstract
Abstract A read/write circuit for a random access memory comprises mode switching means for placing the memory into a read mode if an external read request signal is received and for placing the memory into a write mode if an external write request signal is received. A priority circuit controls said mode switching means and prevents it from placing the memory into the read mode as long as a write request signal is present and enables said mode switching means for placing the memory into the read mode after each write operation has been completed. A read-out control circuit is responsive to the read request signal for enabling a read operation at the next following read mode enabling and for repeating the read operation at the subsequent read mode enabling if the read operation was not completed before the termination of the read mode enabling.
Inventors
- 👤 Dieter Kible
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:22
CPC Classifications
G; G11; G11C; G11C7/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
226 words
A read/write circuit for a random access memory including an output circuit, the read/write circuit comprising: write logic means having an input for receiving a write request signal and coupled to the memory for supplying write signals thereto; switching means having an input for receiving the write request signal and coupled to the memory for selectively supplying write or read address signals to the memory; read logic means, coupled to the switching means and the memory output circuit and having inputs for receiving a read request signal and a read select signal, for initiating the reading of information from the memory in response to a read request signal and a read select signal and for reinitiating the reading of information from the memory in response to a read select signal when the reading of information was previously terminated before completion; and priority circuit means having an input for receiving the write request signal and coupled to the switching means and the read logic means for permitting the switching means to supply a write address signal to the memory, for supplying the read select signal to the read logic means in the absence of a write request signal, and for preventing the initiation of reading of information from the memory and terminating any current reading of information from the memory in response to the write request signal.
Claim 2
Dependent Claim
226 words
A read/write circuit for a random access memory including an output circuit, the read/write circuit comprising: write logic means having an input for receiving a write request signal and coupled to the memory for supplying write signals thereto; switching means having an input for receiving the write request signal and coupled to the memory for selectively supplying write or read address signals to the memory; read logic means, coupled to the switching means and the memory output circuit and having inputs for receiving a read request signal and a read select signal, for initiating the reading of information from the memory in response to a read request signal and a read select signal and for reinitiating the reading of information from the memory in response to a read select signal when the reading of information was previously terminated before completion; and priority circuit means having an input for receiving the write request signal and coupled to the switching means and the read logic means for permitting the switching means to supply a write address signal to the memory, for supplying the read select signal to the read logic means in the absence of a write request signal, and for preventing the initiation of reading of information from the memory and terminating any current reading of information from the memory in response to the write request signal.
Claim 3
Dependent Claim
46 words
A circuit as in claim 1 wherein the priority circuit means comprises a retriggerable monostable multivibrator having a write clock input and an output, having a delay time matched to the duration of a write operation and generating an output signal for driving the switching means.
Claim 4
Dependent Claim
48 words
A circuit as in claim 1 wherein the switching means comprises an address multiplexer having an address input, a control input and an output, the address input of which receives write and read addresses and the output of which is connected to an address input of the memory.
Claim 5
Dependent Claim
24 words
A circuit as in claim 1 wherein the read logic means produces a read confirmation signal if a read operation has been successfully completed.
Claim 6
Dependent Claim
52 words
A circuit as in claim 3 wherein the priority circuit means comprises a retriggerable monostable multivibrator having a write clock input and an output and having a delay time matched to the duration of a write operation, the output being connected to the switching means control input for driving the switching means.
Claim 7
Dependent Claim
46 words
A circuit as in claim 1, 2, 3, 4 or 5 further comprising write control means coupled to the switching means and the priority circuit means for supplying data to and causing it to be written into the memory in response to the write request signal.
Claim 8
Dependent Claim
35 words
A read/write circuit as in claim 1 wherein the memory output circuit comprises a buffer register coupled to the memory and to the read logic means for storing information being read out from the memory.
References Cited (Backward Citations)
US3969706A
Cited
US4141039A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-22 | 1987-02-21 | 1987-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-22 | 1991-02-21 | 1991-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-22 | 1995-02-21 | 1995-08-23 | $7700.00 | Window Closed / Lapsed |