Patent US5002898A successfully refreshed from Google Patents.
US5002898A
Expired / Lapsed
US
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Integrated-circuit device isolation
Assignee: Nokia Bell Labs
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Filing: 1989-10-19
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Granted: 1991-03-26
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Expires: 2009-10-19
Abstract
Abstract In the manufacture of integrated-circuit semiconductor devices, prior to formation of a field oxide, a mask structure is provided on a silicon device area, comprising a pad oxide layer, a polysilicon buffer layer, a protective oxide layer, and a silicon nitride mask layer. Inclusion of the protective layer between polysilicon and silicon nitride layers prevents pad oxide failure and attendant substrate etching during strip-etching of the structure overlying the pad oxide.
Inventors
- 👤 Larry B. Fritzinger
- 👤 Kuo-Hua Lee
- 👤 Chih-Yuan Lu
- 👤 Janmye Sung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:42
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/61; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
126 words
In the manufacture of integrated-circuit semiconductor devices, a method for forming an isolation region on a portion of a planar silicon surface, comprising forming an oxidation mask structure on a first oxide layer on said surface, said structure covering a device region excluded from said planar portion and comprising a buffer layer consisting essentially of silicon, and a mask layer consisting essentially of silicon nitride, forming said isolation region by oxidation of said portion of said planar silicon surface, and removing said structure from said device region by etching, characterized in that, intermediary to said buffer layer and said mask layer a second oxide layer is included, consisting essentially of silicon oxide, whereby, in the course of removing said structure, etching of the surface is inhibited.
Claim 2
Dependent Claim
126 words
In the manufacture of integrated-circuit semiconductor devices, a method for forming an isolation region on a portion of a planar silicon surface, comprising forming an oxidation mask structure on a first oxide layer on said surface, said structure covering a device region excluded from said planar portion and comprising a buffer layer consisting essentially of silicon, and a mask layer consisting essentially of silicon nitride, forming said isolation region by oxidation of said portion of said planar silicon surface, and removing said structure from said device region by etching, characterized in that, intermediary to said buffer layer and said mask layer a second oxide layer is included, consisting essentially of silicon oxide, whereby, in the course of removing said structure, etching of the surface is inhibited.
Claim 3
Dependent Claim
17 words
The method of claim 1 in which removing said structure comprises wet etching of said mask layer.
Claim 4
Dependent Claim
14 words
The method of claim 2 in which wet etching comprises exposure to phosphoric acid.
Claim 5
Dependent Claim
17 words
The method of claim 1 in which removing said structure comprises plasma etching of said buffer layer.
Claim 6
Dependent Claim
15 words
The method of claim 4 in which plasma etching comprises exposure to a chlorine-oxygen plasma.
Claim 7
Dependent Claim
16 words
The method of claim 1 in which said second oxide layer is formed by thermal growth.
Claim 8
Dependent Claim
15 words
The method of claim 1 in which said second oxide layer is formed by deposition.
Claim 9
Dependent Claim
16 words
The method of claim 1 in which said first oxide layer is formed by thermal growth.
Claim 10
Dependent Claim
23 words
The method of claim 1 in which said oxidation mask structure is anisotropically etched in the presence of a photolithographically patterned resist layer.
Claim 11
Dependent Claim
23 words
The method of claim 9 in which anisotropic etching comprises exposure of said mask layer to a plasma comprising Freon 23 and oxygen.
Claim 12
Dependent Claim
22 words
The method of claim 9 in which anisotropic etching comprises exposure of said buffer layer to a plasma comprising chlorine and oxygen.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-25 | 1994-09-24 | 1995-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-25 | 1998-09-24 | 1999-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-25 | 2002-09-24 | 2003-03-26 | $7700.00 | Window Closed / Lapsed |