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US5001533A Expired / Lapsed US ⏱️ 0.0 years remaining

Bipolar transistor with side wall base contacts

Assignee: Toshiba Corp
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Filing: 1989-11-20
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Granted: 1991-03-19
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Expires: 2009-11-20
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Abstract

Abstract A bipolar-type semiconductor device includes a semiconductor substrate on which a collector layer of a first conductivity type, a multilayered structure having a first insulating layer, a first semiconductor layer for connecting a base region, containing an impurity of a second conductivity type, and a second insulating layer, which are sequentially stacked on the semiconductor substrate, in which a first opening is formed in the first semiconductor layer and the second insulating layer, and a second opening having a smaller width than that of the first opening is formed in a position of the first insulating layer corresponding to the bottom portion of the first opening, a second semiconductor layer of the first conductivity type constituting a collector or emitter region formed in the second opening on the impurity-doped layer, a third semiconductor layer of the second conductivity type formed in the first opening, in which a first portion on the second semiconductor layer constitutes a base region, and a second portion adjacent to the first semiconductor layer constitutes a base connecting region, a third insulating layer formed on the base connecting region, and an impurity-doped region of the first conductivity type formed on a surface region of the third semiconductor layer surrounded by the third insulating layer, the impurity-doped region constituting an emitter or collector region.

Inventors

  • 👤 Toshio Yamaguchi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 20:30
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D10/054; H10D10/40; H10D10/441; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/018; H10W10/10

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 205 words
A semiconductor device comprising: a semiconductor substrate on which an impurity-doped layer of a first conductivity type is formed; a multilayered structure including a first insulating layer, a first semiconductor layer for connecting a base region, containing an impurity of a second conductivity type, and a second insulating layer, which are sequentially stacked on said semiconductor substrate, in which a first opening is formed in said first semiconductor layer and said second insulating layer, and a second opening having a smaller width than that of said first opening is formed in a position of said first insulating layer corresponding to the bottom portion of said first opening; a second semiconductor layer of the first conductivity type formed in said second opening on said impurity-doped layer; a third semiconductor layer of the second conductivity type formed in said first opening, in which a first portion on said second semiconductor layer constitutes a base region and a second portion adjacent to said first semiconductor layer constitutes a base connecting region; a third insulating layer formed on said base connecting region; and an impurity-doped region of the first conductivity type formed in a surface region of said third semiconductor layer, which is surrounded by said third insulating layer.
Claim 2
Dependent Claim 205 words
A semiconductor device comprising: a semiconductor substrate on which an impurity-doped layer of a first conductivity type is formed; a multilayered structure including a first insulating layer, a first semiconductor layer for connecting a base region, containing an impurity of a second conductivity type, and a second insulating layer, which are sequentially stacked on said semiconductor substrate, in which a first opening is formed in said first semiconductor layer and said second insulating layer, and a second opening having a smaller width than that of said first opening is formed in a position of said first insulating layer corresponding to the bottom portion of said first opening; a second semiconductor layer of the first conductivity type formed in said second opening on said impurity-doped layer; a third semiconductor layer of the second conductivity type formed in said first opening, in which a first portion on said second semiconductor layer constitutes a base region and a second portion adjacent to said first semiconductor layer constitutes a base connecting region; a third insulating layer formed on said base connecting region; and an impurity-doped region of the first conductivity type formed in a surface region of said third semiconductor layer, which is surrounded by said third insulating layer.
Claim 3
Dependent Claim 23 words
A device according to claim 1, wherein said second semiconductor layer is a collector region, and said impurity-doped region is an emitter region.
Claim 4
Dependent Claim 23 words
A device according to claim 1, wherein said second semiconductor layer is an emitter region, and said impurity-doped region is a collector region.
Claim 5
Dependent Claim 15 words
A device according to claim 1, wherein said first semiconductor layer consists of polycrystalline silicon.
Claim 6
Dependent Claim 15 words
A device according to claim 1, wherein said base connecting region consists of polycrystalline silicon.
Claim 7
Dependent Claim 26 words
A device according to claim 1, wherein said first insulating layer consists of a multilayered structure including a silicon oxide layer and a silicon nitride layer.

References Cited (Backward Citations)

JPS561556A Cited
JPS59217364A Cited
US4710241A Cited
JPS61208872A Cited
US4797372A Cited
US4782030A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-03-18 1994-09-17 1995-03-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-03-18 1998-09-17 1999-03-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-03-18 2002-09-17 2003-03-19 $7700.00 Window Closed / Lapsed

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