Semiconductor integrated circuit device

Claim 1

A semiconductor integrated circuit device comprising: (1) basic cells, each formed at predetermined area of semiconductor substrate, and each including a first and a second MOSFETs including a gate electrode and semiconductor regions serving as a pair of source and drain regions, respectively, and a pair of bipolar transistors; (2) basic cell arrays, each formed by disposing a plurality of said basic cells in a predetermined direction; (3) a basic cell matrix formed by disposing a plurality of said basic cell arrays in a direction substantially perpendicular to said predetermined direction and with predetermined gaps between them; and (4) a first operating potential line and a second operating potential line extending along said basic cell array substantially in parallel with said predetermined direction so as to pass opposite peripheries of each of said basic cells, and which are connected to selected ones of said bipolar transistors, wherein each of said bipolar transistors of said pair of bipolar transistors are respectively arranged at said opposite peripheries in said basic cell and said semiconductor regions serving as said pair of source and drain regions of said first and second MOSFETs are arranged substantially at a center portion of said basic cell, and wherein said gate electrode of said first MOSFET is extended so s to intersect said first and/or second operating potential lines and said gate electrode of said second MOSFET is extended between said pair of bipolar transistors so that both end portions of said gate electrode of said second MOSFET are arranged between said pair of bipolar transistors.