Macrocell array having an on-chip clock generator

Claim 1

A macrocell array comprising: a plurality of cells, each of said cells having a plurality of semiconductor devices, said semiconductor devices being interconnected within each cell to provide logic functions; a plurality of input/output pads, each adapted to receive an input signal; a plurality of horizontal routing channels within one or more metallization layers overlying said cells, said horizontal routing chennels being coupled to said plurality of semiconductor devices at selected input/output points of said logic functions; a plurality of vertical routing channels within said one or more metallization layers overlying said cells, said vertical routing channels coupled to said horizontal routing channels and said input/output pads; a clock generator included within one of said plurality of cells, comprising: gate means coupled to one of said plurality of input/output pads and responsive to an input signal, and having a delayed signal as an output; a first transistor having a base coupled to a first reference voltage; a second transistor having a base coupled to said one of said plurality of input/output pads and differentially connected to said first transistor; a third transistor having a base coupled to said gate means and responsive to said delayed signal, and differentially connected to said first transistor; a fourth transistor having a base coupled to a collector of said first transistor and an emitter coupled to an output terminal for providing an output signal; and a fifth transitor having a base adapted to receive an external override high signal and differentially connected to said first transistor for controlling said output signal regardless of said input signal; and means coupled to said base of said fourth transistor and adapted to receive an external override low signal for controlling said output signal regardless of said input signal and said external override high signal.