Patent US2070244A successfully refreshed from Google Patents.
Patent US5001073A successfully refreshed from Google Patents.
US5001073A
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US
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Method for making bipolar/CMOS IC with isolated vertical PNP
Assignee: Allegro Microsystems LLC
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Filing: 1990-07-16
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Granted: 1991-03-19
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Expires: 2010-07-16
Abstract
Abstract The manufacture of an integrated circuit including an isolated vertical PNP, an isolated vertical NPN and isolated CMOS transistors is described. The PNP transistor has a shallow densely doped emitter made simultaneously with the source and drain of the PMOS transistor. The PNP base is made simultaneously with lightly doped portions of the LDD source and drain of the NMOS transistor. The PNP collector is made simultaneously with the P-well in which the NMOS transistor is formed. A P-buried layer in the isolated vertical PNP transistor provides a low collector resistance and is formed simultaneously with the P-buried layer of the NMOS transistor that extends the P-well there and better isolates the NMOS transistor from the substrate. And the N-buried layer providing superior isolation of the PNP with respect to the substrate is formed simultaneously with the N-buried layer of the vertical NPN transistor. All four of these transistors provide and are well suited for use in analog signal handling circuits. All are capable of operating at up to 15 volts. And both bipolar transistors have a high gain bandwidth.
Inventors
- 👤 Wing K. Huie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:50
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; Y; Y10; Y10S; Y10S148/00; Y10S148/009
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
308 words
A method for making an integrated circuit comprising growing an N-type epitaxial layer over a major surface of a P-type silicon substrate; forming a network of P-type isolation walls in said epitaxial layer to define first, second and third epitaxial pockets of N-epitaxial material wherein an isolated vertical PNP transistor, an isolated vertical NPN transistor and a pair of CMOS transistors are to be formed, respectively: forming one N+ buried layer in said first pocket; selectively implanting a P-type dopant into said first and a part of said third epitaxial pockets and heating said substrate to drive said P-type dopant to form one P-well to serve as the collector of said vertical PNP transistor in said first pocket and to form in said third pocket another P-well in which the NMOS transistor of said CMOS transistors is to be formed; forming one discrete conductive film in said third pocket over a part of said another P-well to serve as the gate of said NMOS transistor, and another discrete conductive film over a part of said third pocket that is of N-epitaxial material, and to one side of said another P-well, to serve as the gate of the PMOS transistor of said CMOS transistors: selectively implanting N-type ions in one implanting step into a portion of said one P-well in said first epitaxial pocket and into two small portions of said another P-well in said third epitaxial pocket, which small portions lie on opposite sides of and adjacent to said NMOS transistor gate, and heating to drive said N-type ions deeper into said first epitaxial pocket and partially into said one P-well, respectively, to simultaneously form the N-base of said PNP transistor and to form lightly doped parts of the source and the drain of said NMOS transistor on opposite sides of and adjacent to said NMOS transistor gate.
Claim 2
Independent Claim
308 words
A method for making an integrated circuit comprising growing an N-type epitaxial layer over a major surface of a P-type silicon substrate; forming a network of P-type isolation walls in said epitaxial layer to define first, second and third epitaxial pockets of N-epitaxial material wherein an isolated vertical PNP transistor, an isolated vertical NPN transistor and a pair of CMOS transistors are to be formed, respectively: forming one N+ buried layer in said first pocket; selectively implanting a P-type dopant into said first and a part of said third epitaxial pockets and heating said substrate to drive said P-type dopant to form one P-well to serve as the collector of said vertical PNP transistor in said first pocket and to form in said third pocket another P-well in which the NMOS transistor of said CMOS transistors is to be formed; forming one discrete conductive film in said third pocket over a part of said another P-well to serve as the gate of said NMOS transistor, and another discrete conductive film over a part of said third pocket that is of N-epitaxial material, and to one side of said another P-well, to serve as the gate of the PMOS transistor of said CMOS transistors: selectively implanting N-type ions in one implanting step into a portion of said one P-well in said first epitaxial pocket and into two small portions of said another P-well in said third epitaxial pocket, which small portions lie on opposite sides of and adjacent to said NMOS transistor gate, and heating to drive said N-type ions deeper into said first epitaxial pocket and partially into said one P-well, respectively, to simultaneously form the N-base of said PNP transistor and to form lightly doped parts of the source and the drain of said NMOS transistor on opposite sides of and adjacent to said NMOS transistor gate.
Claim 3
Dependent Claim
37 words
The method of claim 1 additionally comprising selectively implanting N-type ions to form a double diffused surface portion of said NMOS source and drain that is more heavily N-doped and shallower than said lightly doped N-doped parts.
Claim 4
Dependent Claim
59 words
The method of claim 1 additionally comprising selectively implanting P-type ions into a surface portion of said N-base region of said PNP transistor, and annealing at a mildly elevated temperature to form a shallow heavily doped P-type emitter of said PNP transistor and to provide a narrow base width of said PNP transistor of from 0.2 to 0.4 micron.
Claim 5
Dependent Claim
38 words
The method of claim 1 additionally comprising forming a P-doped buried layer in said first epitaxial pocket extending out of said N+ buried layer further into said first epitaxial pocket and into overlapping relationship with said one P-well.
Claim 6
Dependent Claim
30 words
The method of claim 4 wherein said forming said one P-doped buried layer additionally includes simultaneously forming another P-doped buried layer in said third epitaxial pocket under said NMOS transistor.
Claim 7
Dependent Claim
36 words
The method of claim 1 additionally comprising implanting P-type ions selectively into the field regions peripheral of said PNP, NPN, NMOS and PMOS transistors to form a P-type channel stop region peripheral of said NMOS transistor.
Claim 8
Dependent Claim
76 words
The method of claim 6 additionally comprising masking off PNP transistor and surrounding field region and said NMOS transistor and surrounding field region, and implanting N-type ions into the field regions peripheral of said NPN and PMOS transistors to form net-N-type channel stops peripheral of said NPN and PMOS transistors, respectively, and to form peripheral of said PNP transistor a net-N-type region peripheral of said one P-well for increasing the breakdown voltage of said PNP transistor.
Claim 9
Dependent Claim
70 words
The method of claim 1 additionally comprising forming a P-type base in said second epitaxial pocket; and implanting in one step a heavy dose of N-type ions selectively in said first, second and third epitaxial pockets for form the base contact region in said PNP transistor, to form a heavily doped source portion and drain portion of NMOS transistor and provide double diffused sources and drains in said NMOS transistor.
Claim 10
Dependent Claim
26 words
The method of claim 1 additionally comprising forming a second N+ buried layer in said second pocket simultaneously with said forming said one N+ buried layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-18 | 1994-09-17 | 1995-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-18 | 1998-09-17 | 1999-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-18 | 2002-09-17 | 2003-03-19 | $7700.00 | Window Closed / Lapsed |