High-precision and high-speed analog/digital converter having low power consumption

Claim 2

An analog/digital converter comprising: a first comparator group, in which each comparator is constituted by bipolar transistors, for comparing a plurality of different primary reference voltages with an analog input voltage; a latch circuit group having a latch circuit which is constituted by MOS transistors, for latching comparison results of said first comparator group; means for obtaining a first digital converted value corresponding to the analog input voltage, in accordance with storage contents of said latch circuit group; selecting means for selecting a high-level primary reference voltage approximate to the analog input voltage and a low-level primary reference voltage, in accordance with the storage contents of said latch circuit group; secondary reference voltage generating means for dividing a potential difference between the high-level and the low-level primary reference voltages selected by said selecting means, to generate a plurality of secondary reference voltages generated by a primary voltage generating means; a second comparator group, in which each comparator is constituted by bipolar transistors, for comparing the plurality of secondary reference voltages generated by said secondary reference voltage generating means with the analog input voltage; means for obtaining a second digital converted value corresponding to the analog input voltage, in accordance with comparison results of said second comparator group; and means for obtaining a digital converted value corresponding to the analog input voltage, in accordance with the first and second digital converted values.

Claim 3

The p-channel MOS transistors 61 and 62 constitute a disconnecting circuit for disconnecting the latch circuit 60 and the voltage comparator 11 while the CMOS latch 69 latches the signals Q1 and Q1.

Claim 4

The p-channel MOS transistors 61 and 62 constitute a disconnecting circuit for disconnecting the latch circuit 60 and the voltage comparator 11 while the CMOS latch 69 latches the signals Q1 and Q1.

Claim 5

An analog/digital converter comprising: primary reference voltage generating means for generating a plurality of different primary reference voltages; a first comparator group, in which each comparator is constituted by bipolar transistors, for comparing the plurality of different primary reference voltages with an analog input voltage; a latch circuit group having a latch circuit which is constituted by MOS transistors, for latching comparison results of said first comparator group; means for obtaining a first digital converted value corresponding to the analog input voltage, in accordance with storage contents of said latch circuit group; selecting means for selecting a high-level primary reference voltage approximate to the analog input voltage and a low-level primary reference voltage, in accordance with the storage contents of said latch circuit group; secondary reference voltage generating means for dividing a potential difference between the high-level and the low-level primary reference between the high-level and the low-level primary reference voltages selected by said selecting means, to generate a plurality of secondary reference voltages; a secondary comparator group, in which each comparator is constituted by bipolar transistors, for comparing the plurality of secondary reference voltages with the analog input voltage; first means for obtaining a second digital converted value corresponding to the analog input voltage, in accordance with comparison results of said second comparator group; level converting means for converting a bipolar level output from said first means into a CMOS level; and second means for obtaining a digital converted value corresponding to the analog input voltage, in accordance with the first and second digital converted values.

Claim 6

An analog/digital converter comprising: primary reference voltage generating means for generating a plurality of different primary reference voltages; a first comparator group, in which each comparator is constituted by bipolar transistors, for comparing the plurality of different primary reference voltages with an analog input voltage; a latch circuit group having a latch circuit which is constituted by MOS transistors, for latching comparison results of said first comparator group; means for obtaining a first digital converted value corresponding to the analog input voltage, in accordance with storage contents of said latch circuit group; selecting means for selecting a high-level primary reference voltage approximate to the analog input voltage and a low-level primary reference voltage, in accordance with the storage contents of said latch circuit group; secondary reference voltage generating means for dividing a potential difference between the high-level and the low-level primary reference between the high-level and the low-level primary reference voltages selected by said selecting means, to generate a plurality of secondary reference voltages; a secondary comparator group, in which each comparator is constituted by bipolar transistors, for comparing the plurality of secondary reference voltages with the analog input voltage; first means for obtaining a second digital converted value corresponding to the analog input voltage, in accordance with comparison results of said second comparator group; level converting means for converting a bipolar level output from said first means into a CMOS level; and second means for obtaining a digital converted value corresponding to the analog input voltage, in accordance with the first and second digital converted values.

Claim 7

An analog/digital converter according to claim 3 wherein the latch circuit of said latch circuit group includes a disconnecting circuit which disconnects a connection between each comparator of said first comparator group and the latch circuit while said latch circuit latches said comparison result of said first comparator group.