Analogue-to-digital converter with controlled analogue setting

Claim 1

A high-speed encoder of the series-parallel type for converting analogue input voltages into combinations of bits, comprising: a first and a second encoder section respectively including a first group of comparators and a second group of comparators each having a test input and a reference input; a source of first threshold voltages, separated by relatively large increments ΔV1, respectively applied to the reference inputs of said first group of comparators; a source of second threshold voltages, separated by relatively small increments ΔV2, respectively applied to the reference inputs of said second group of comparators; first circuit means for feeding an analogue input voltage in parallel to the test inputs of all the comparators of said first group with resulting generation of a set of higher-order bits in an output of said first encoder section; second circuit means for feeding said analogue input voltage in parallel and with a predetermined delay to the test inputs of all the comparators of said second group with resulting generation of a set of lower-order bits in an output of said second encoder section, each comparator of said second group responding to a predetermined relationship between the voltages on its test and reference inputs by changing from an unswitched state with flow of biasing current in its reference input to a switched state with flow of biasing current in its test input; and a control network including digital-to-analogue conversion means connected to the output of said first encoder section for concurrently shifting said second threshold voltages in response to said higher-order bits to hold said analogue input voltage within the operating ranges of said second group of comparators, said source of second threshold voltages including a resistive voltage divider connected in series with a fixed resistor R across a constant-current generator and consisting of p segments of resistance r forming p junctions with one another and with said fixed resistor, p being the number of comparators in said second group, said junctions being respectively connected to the reference inputs of the comparators of said second group, said control network being in series with said fixed resistor only for modifying the voltage drop thereacross by multiples of ΔV1, the current I delivered by said generator being less than a current Io required to make the total voltage drop prI across said voltage divider equal to ΔV1, the difference Io - I substantially compensating for threshold errors due to said biasing currents.