High speed parallel-cascaded analog to digital connector

Claim 2

A parallel-cascaded analog to digital converter for converting an analog input signal to a 2N bit digital output signal, comprising: a first parallel analog to digital converter receiving and converting the analog input signal to a first N bit digital output signal comprising the more significant bits of the 2N bit digital output signal, a summer, a constant current source, a second parallel analog to digital converter receiving and converting the analog input signal to a second N bit digital output signal comprising the lesser significant bits of the 2N bit digital output signal, said second analog to digital converter including reference voltage level establishing means connected in circuit with said summer means and energized by said constant current source for establishing a range of reference voltage levels. current switching means connected in circuit with said summer and responsive to the first N bit output signal to control the current flow in said summer for selectively establishing voltages of predetermined levels across said summer said voltages of predetermined levels, respectively corresponding to the bit values of the first N bit output signal, and correspondingly selectively varying the range of reference voltage levels established by said reference voltage establishing means.

Claim 3

A parallel-cascaded analog to digital converter as recited in claim 1, wherein said summer comprises a resistor.

Claim 4

A parallel-cascaded analog to digital converter as recited in claim 1, wherein said reference voltage level establishing means comprises a resistor divider network.

Claim 5

A parallel-cascaded analog to digital converter as recited in claim 3, wherein: said resistor divider network is connected in series with said summer resistor, and said current switching means is connected to the series connection of said resistor divider network and said summer resistor.

Claim 6

A parallel-cascaded analog to digital converter as recited in claim 4, wherein there are provided: N current switching means respectively receiving corresponding ones of the first N bit digital outputs, and said N current switching means are connected in parallel to said series connection of said resistor divider network and said summer resistor.

Claim 7

A parallel-cascaded analog to digital converter as recited in claim 5, wherein said current switching means, from the least to the most significant bit of the first N bit digital outputs, respectively conduct a current 2nI where n 0, 1, . . . N.

Claim 8

A parallel-cascaded analog to digital converter as recited in claim 6, wherein said constant current source provides a current I, said summer resistor has a resistance RT and the voltage E0 across the summer resistor is defined by:

Claim 9

A parallel-cascaded analog to digital converter as recited in claim 4, wherein successive reference voltage levels established by said resistor divider network differ by the analog voltage equivalent of the least significant bit output of the second analog to digital converter.

Claim 10

A parallel-cascaded analog to digital converter for converting an analog input signal to a 2N bit digital output signal, comprising: a first parallel analog to digital converter receiving and converting the analog input signal to a first N bit digital output signal comprising the more significant bits of the 2N bit digital output signal, a summer, a constant current source, a second parallel analog to digital converter receiving and converting the analog input signal to a second bit digital output signal comprising the lesser significant bits of the 2N bit digital output signal, said second analog to digital converter including reference voltage level establishing means connected in circuit with said summer means and said constant current source to be energized thereby for establishing 2N reference voltage levels differing in value by the equivalent analog value of the least significant bit output of the second analog to digital converter over a first range set by the voltage drop through said summer in response to the constant current, N current switching means receiving corresponding ones of the N bit outputs of said first analog to digital converter and being individually switched to a conducting or a non-conducting state in accordance with the values of the respective bits, and said N switching means being connected in parallel to said summer and being independently operative in the conducting states thereof as current sinks for selectively conducting currents of corresponding, predetermined magnitudes through said summer and producing corresponding, predetermined voltage drops across said summer for setting corresponding, different ranges of reference voltage levels.

Claim 11

A parallel-cascaded analog to digital converter for converting an analog input signal to a 2N bit digital output signal, comprising: a first parallel analog to digital converter receiving and converting the analog input signal to a first N bit digital output signal comprising the more significant bits of the 2N bit digital output signal, a summer, a constant current source, a second parallel analog to digital converter receiving and converting the analog input signal to a second bit digital output signal comprising the lesser significant bits of the 2N bit digital output signal, said second analog to digital converter including reference voltage level establishing means connected in circuit with said summer means and said constant current source to be energized thereby for establishing 2N reference voltage levels differing in value by the equivalent analog value of the least significant bit output of the second analog to digital converter over a first range set by the voltage drop through said summer in response to the constant current, N current switching means receiving corresponding ones of the N bit outputs of said first analog to digital converter and being individually switched to a conducting or a non-conducting state in accordance with the values of the respective bits, and said N switching means being connected in parallel to said summer and being independently operative in the conducting states thereof as current sinks for selectively conducting currents of corresponding, predetermined magnitudes through said summer and producing corresponding, predetermined voltage drops across said summer for setting corresponding, different ranges of reference voltage levels.

Claim 12

A parallel-cascaded analog to digital converter as recited in claim 9, wherein said current switching means, from the least to the most significant bit of the first N digital outputs, respectively conduct a current 2nI where n 0, 1, . . . N.

Claim 13

A parallel-cascaded analog to digital converter as recited in claim 10, wherein said constant current source provides a current I, said summer resistor has a resistance RT and the voltage E0 across the summer resistor is defined by: