Pcm coder with compression characteristic

Abstract

Abstract Analog signals within a predetermined amplitude range are subjected, in a first amplifier stage, to parallel amplification with a relatively low gain (e.g. unity) and with a relatively high gain (e.g. 16:1) and are simultaneously rectified to have a single polarity (e.g. positive); the voltages on the four output leads of this stage are fed in parallel to a first analog/digital converter and, via a second amplifier stage, to a second analog/digital converter for temporary storage in a first and a second binary register, respectively. The first converter, which together with the first register forms part of a precoder, operates according to a reflected code (Gray code) to generate a sign bit, indicating the polarity of the incoming analog signal, and a group of m higher-order bits (e.g. m 3) specifying 2m positive or negative amplitude bands; these m+1 bits are delivered to a logic network which controls the operation of a selector switch unblocking one of the output leads of the first amplifier stage and which also modifies the gain of the second amplifier stage to make the voltage swing in its output identical for all 2m bands of either polarity. The second converter, also operating in a reflected code, generates a group of n lower-order bits (e.g. n 4) giving the amplitude increments or quanta within each band. The contents of both registers may be read out through further code converters translating the reflected code into the natural binary code. The selector switch normally grounds the input of the second amplifier stage to which the output voltage of the first amplifier stage is transmitted with a delay matching the interval between a writing pulse for the first register and a similar pulse for the second register; the latter pulse restores the selector switch to normal after a limited transfer period.

Inventors

• 👤 W Fruhauf

Bibliographic Details