US4752766A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog to digital converter
Assignee: Hitachi Ltd
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Filing: 1987-02-17
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Granted: 1988-06-21
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Expires: 2007-02-17
Abstract
Abstract In an analog-to-digital converter of a parallel comparison type having a plurality of comparators for comparing an analog input voltage with different reference voltages and converting a comparison result into a digital output by means of an encoder, a plurality of comparators each having a different input dynamic range are used to widen the analog input voltage range up to the power source range of positive and negative voltages.
Inventors
- 👤 Toshihiko Shimizu
- 👤 Masao Hotta
- 👤 Kenji Maio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:04
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/36; H03M1/361
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
149 words
A parallel comparison type analog-to-digital converter comprising: a group of resistors each of which is connected in series for dividing a voltage applied across both end terminals of said group of resistors to generate a plurality of reference voltages; a plurality of comparators for comparing an analog input voltage with each of said reference voltages; and an encoder for converting the outputs from said plurality of comparators into a digital output, wherein said plurality of comparators are divided into at least two groups based on the level of the inputted reference voltages to be compared with said analog input voltage, such that a first group of said plurality of comparators which correspond to a first level of reference voltages have a wider voltage dynamic range than a second group of said plurality of comparators, said second level of reference voltages being lower than said first level of reference voltages.
Claim 2
Dependent Claim
149 words
A parallel comparison type analog-to-digital converter comprising: a group of resistors each of which is connected in series for dividing a voltage applied across both end terminals of said group of resistors to generate a plurality of reference voltages; a plurality of comparators for comparing an analog input voltage with each of said reference voltages; and an encoder for converting the outputs from said plurality of comparators into a digital output, wherein said plurality of comparators are divided into at least two groups based on the level of the inputted reference voltages to be compared with said analog input voltage, such that a first group of said plurality of comparators which correspond to a first level of reference voltages have a wider voltage dynamic range than a second group of said plurality of comparators, said second level of reference voltages being lower than said first level of reference voltages.
Claim 3
Dependent Claim
48 words
An analog-to-digital converter according to claim 1, wherein each comparator in said comparator group comprises a latching comparator section whose sampling operation and latching operation are switched in response to a clock signal supplied thereto, said latching comparator being provided at a preceding stage with a pre-amplifier section.
Claim 4
Dependent Claim
34 words
An analog-to-digital converter according to claim 2, wherein said pre-amplifier section of said comparator comprises an emitter follower stage for shifting a level of said analog input and a differential amplifier stage connected thereto.
Claim 5
Dependent Claim
44 words
An analog-to-digital converter according to claim 3, wherein said emitter follower stage of said pre-amplifier section of at least one comparator of said plurality of comparator groups comprises an emitter follower including an NPN transistor and a current source connected to said emitter follower.
Claim 6
Dependent Claim
23 words
An analog-to-digital converter according to claim 4, wherein said current source is a constant current source including an NPN transistor and a resistor.
Claim 7
Dependent Claim
48 words
An analog-to-digital converter according to claim 3, wherein said emitter follower stage of said pre-amplifier section of at least one comparator of said plurality of comparator groups comprises an emitter follower made of a PNP transistor and a current source connected to the emitter of said emitter follower.
Claim 8
Dependent Claim
44 words
An analog-to-digital converter according to claim 3, wherein said emitter follower stage of said pre-amplifier section of at least one comparator of said plurality of comparator groups comprises an emitter follower and a plurality of diodes connected to the emitter of said emitter follower.
Claim 9
Dependent Claim
23 words
An analog-to-digital converter according to claim 6, wherein said current source is a constant current source including a PNP transistor and a resistor.
References Cited (Backward Citations)
US4400693A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-21 | 1991-12-21 | 1992-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-21 | 1995-12-21 | 1996-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-21 | 1999-12-21 | 2000-06-21 | $7700.00 | Window Closed / Lapsed |