Apparatus for synchronizing clock signals

Claim 1

Apparatus for synchronising a clock signal to a pulse, the apparatus comprising: a clock signal generator for generating a first clock signal having a frequency equal to that of a desired clock signal; a shift register having a serial input port connected to said clock signal generator and a number of parallel output ports, for generating a number of time delayed versions of said first clock signal, each said time delay being less than the period of said first clock signal; comparison means for comparing said time delayed versions of said first clock signal and said original clock signal at the time of occurrence of said pulse and for selecting as said desired clock signal, a version of said first clock signal which has changed state close to the time of occurrence of said pulse; and frequency multiplier means, receiving said first clock signal, for generating a second clock signal having a frequency higher than said first clock signal, said second clock signal controlling the shift rate of said shift register, wherein each of said parallel output ports of said shift register is connected to said comparison means to provide said time delayed versions of said first clock signal.