Patent US4625547A successfully refreshed from Google Patents.
Patent US4999318A successfully refreshed from Google Patents.
US4999318A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming metal layer interconnects using stepped via walls
Assignee: Hitachi Ltd
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Filing: 1989-07-06
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Granted: 1991-03-12
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Expires: 2009-07-06
Abstract
Abstract A method for forming vias, interconnecting selected wiring layers of an integrated circuit device, which overcomes oxide formation on the wiring metal surface which is exposed at the etched via bottom before filling the via with interconnecting metal. The method first etches the vias through the insulating layer, with a step or stair like wall formation, to expose the underlying metal surface. The exposed metal surface is then sputter etched to remove the undesired oxide layer which forms on the metal surface at the via bottom after being exposed by the etch through process. During the sputter etch oxide removal process, the stair like via wall prevents re-oxidation of the exposed metal surface by stray silicon oxide particles dislodged from the via wall during the sputter process.
Inventors
- 👤 Tokunaga Takahumi
- 👤 Tsuneoka Masatoshi
- 👤 Akimori Hiroyuki
- 👤 Horiuch Mitsuaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:25
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/262; H10W20/01; H10W20/071; H10W20/081; Y; Y10; Y10S; Y10S438/00; Y10S438/978
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
255 words
A method of manufacturing a semiconductor integrated circuit device comprising the steps of: (a) preparing a semiconductor substrate having a main surface; (b) forming a plurality of semiconductor elements on said main surface; (c) forming a first inter-layer insulator film over a plurality of said semiconductor elements; (d) forming a first contact hole in said first inter-layer insulator film; (e) forming a first wiring layer on said first inter-layer insulator film, said first wiring layer being made of a material whose principal component is aluminum and being electrically connected with at least one of said semiconductor elements via said first contact hole; (f) forming a second inter-layer insulator film over said first wiring layer; (g) forming a second contact hole in said second inter-layer insulator film by etching to an upper surface of said first wiring layer, a sectional shape of said second contact hole being a configuration which has a plurality of stair-like steps along each of peripheral walls of said second contact hole, said stair-like steps being formed by first peripheral wall planes extending in a vertical direction and a second peripheral wall plane extending in a horizontal direction, said each first peripheral wall plane and said second peripheral wall plane defining an angle of substantially 90 degrees; (h) after step (g), sputter-etching at least said exposed upper surface of said first wiring layer; (i) forming a second wiring layer on said second inter-layer insulator film, said second wiring layer being electrically connected with said first wiring layer via said second contact hole.
Claim 2
Independent Claim
255 words
A method of manufacturing a semiconductor integrated circuit device comprising the steps of: (a) preparing a semiconductor substrate having a main surface; (b) forming a plurality of semiconductor elements on said main surface; (c) forming a first inter-layer insulator film over a plurality of said semiconductor elements; (d) forming a first contact hole in said first inter-layer insulator film; (e) forming a first wiring layer on said first inter-layer insulator film, said first wiring layer being made of a material whose principal component is aluminum and being electrically connected with at least one of said semiconductor elements via said first contact hole; (f) forming a second inter-layer insulator film over said first wiring layer; (g) forming a second contact hole in said second inter-layer insulator film by etching to an upper surface of said first wiring layer, a sectional shape of said second contact hole being a configuration which has a plurality of stair-like steps along each of peripheral walls of said second contact hole, said stair-like steps being formed by first peripheral wall planes extending in a vertical direction and a second peripheral wall plane extending in a horizontal direction, said each first peripheral wall plane and said second peripheral wall plane defining an angle of substantially 90 degrees; (h) after step (g), sputter-etching at least said exposed upper surface of said first wiring layer; (i) forming a second wiring layer on said second inter-layer insulator film, said second wiring layer being electrically connected with said first wiring layer via said second contact hole.
Claim 3
Dependent Claim
36 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said step (h) includes a step of removing a layer of alumina film formed on said first wiring layer by said sputter-etching.
Claim 4
Dependent Claim
30 words
A method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein said layer of alumina film is formed by a surface oxidation of said first wiring layer.
Claim 5
Dependent Claim
24 words
A method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein said layer of alumina is Al 2 O 3 film.
Claim 6
Dependent Claim
24 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said second inter-layer insulator film is a silicon dioxide film.
Claim 7
Dependent Claim
37 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said second inter-layer insulator film is composed of a silicon nitride film and a silicon dioxide film formed on said silicon nitride film.
Claim 8
Dependent Claim
29 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a plane shape of said second contact hole is a configuration which has a square.
Claim 9
Dependent Claim
29 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a plane shape of said second contact hole is a configuration which has a circle.
Claim 10
Dependent Claim
28 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said second wiring layer is made of a material whose principal component is aluminum.
Claim 11
Dependent Claim
23 words
A method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein said second wiring layer is formed by bias sputtering.
Claim 12
Dependent Claim
21 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said semiconductor elements include a bipolar transistor.
Claim 13
Dependent Claim
29 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said stair-like steps is formed along a whole peripheral wall of said second contact hole.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-11 | 1994-09-10 | 1995-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-11 | 1998-09-10 | 1999-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-11 | 2002-09-10 | 2003-03-12 | $7700.00 | Window Closed / Lapsed |