Patent US4994889A successfully refreshed from Google Patents.
US4994889A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1987-12-02
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Granted: 1991-02-19
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Expires: 2007-12-02
Abstract
Abstract A semiconductor memory device includes a memory cell array comprised of a plurality of memory cells each having a single transfer transistor and a single capacitor and a peripheral circuit including a plurality of drive transistors and adapted to drive the memory cell. The source and drain regions of the transfer transistor have an impurity concentration lower in level than that of the source and drain regions of the drive transistor.
Inventors
- 👤 Yukio Takeuchi
- 👤 Satoshi Shinozaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:39
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/01; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10P; H10P14/00; H10P14/40; H10P14/412; H10P32/00; H10P32/30; H10P32/302
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
218 words
A semiconductor memory device comprising: a semiconductor substrate on which a memory cell array and a peripheral circuit area for driving the memory cell array are provided; said memory cell array including a plurality of memory cells each comprised of a single transfer transistor, comprised of source and drain regions and a gate, and a single capacitor; said peripheral circuit area including a peripheral circuit including at least one driver transistor comprised of source and drain regions and a gate, said peripheral circuit being operatively coupled to said plurality of memory cells to drive said plurality of memory cells; a bit line formed of a polysilicon film or metal silicide, said bit line being formed in contact with one of said source and drain regions of the transfer transistor of at least one of said memory cells; wherein said source and drain regions of the transfer transistor in said memory cell have a low impurity concentration that precludes formation of a natural oxide film on a surface of the one of said source and drain regions in contact with said bit line; and wherein the source and drain regions of the transfer transistor in the memory cell have an impurity concentration lower than that of the source and drain regions of the driver transistor of said peripheral circuit.
Claim 2
Dependent Claim
218 words
A semiconductor memory device comprising: a semiconductor substrate on which a memory cell array and a peripheral circuit area for driving the memory cell array are provided; said memory cell array including a plurality of memory cells each comprised of a single transfer transistor, comprised of source and drain regions and a gate, and a single capacitor; said peripheral circuit area including a peripheral circuit including at least one driver transistor comprised of source and drain regions and a gate, said peripheral circuit being operatively coupled to said plurality of memory cells to drive said plurality of memory cells; a bit line formed of a polysilicon film or metal silicide, said bit line being formed in contact with one of said source and drain regions of the transfer transistor of at least one of said memory cells; wherein said source and drain regions of the transfer transistor in said memory cell have a low impurity concentration that precludes formation of a natural oxide film on a surface of the one of said source and drain regions in contact with said bit line; and wherein the source and drain regions of the transfer transistor in the memory cell have an impurity concentration lower than that of the source and drain regions of the driver transistor of said peripheral circuit.
Claim 3
Dependent Claim
55 words
A semiconductor memory device according to claim 1, further comprising: a contact region formed by an impurity diffusion from said polysilicon film or metal silicide and permitting ohmic contact to be made between the bit line and the one of said source and drain regions of the transfer transistor in contact with said bit line.
Claim 4
Dependent Claim
86 words
A semiconductor memory device according to claim 2, in which each of the source and drain regions of the drive transistor of said peripheral circuit has a high impurity region and a low impurity region formed in contact with said high impurity region and said source and drain regions of the transfer transistor in said memory cell are formed to have the same impurity concentration as that of the low impurity regions of said source and drain regions of said driver transistor in said peripheral circuit.
Claim 5
Dependent Claim
90 words
A semiconductor memory device according to claim 3, in which a capacitor in said memory cell includes an insulating layer formed on a surface of said substrate such that it is situated adjacent one of source and drain regions of said transfer transistor in said memory cell and a conductive layer formed as one plate of the capacitor on the insulating layer to cover a part of said substrate which forms the other plate of said capacitor and which is in contact with said one of source and drain regions.
Claim 6
Dependent Claim
73 words
A semiconductor memory device according to claim 4, in which said memory cell includes a first region of the other conductivity type formed in the surface portion of the substrate in contact with said one of source and drain regions of the transfer transistor in said memory cell and in opposition to said conductive layer and a second region of one conductivity type formed in contact with an undersurface of said first region.
Claim 7
Dependent Claim
90 words
A semiconductor memory device according to claim 2 in which a capacitor in said memory cell includes an insulating layer formed on a surface of said substrate such that it is situated adjacent one of source and drain regions of said transfer transistor in said memory cell and a conductive layer formed as one plate of the capacitor on the insulating layer to cover a part of said substrate which forms the other plate of said capacitor and which is in contact with said one of source and drain regions.
Claim 8
Dependent Claim
73 words
A semiconductor memory device according to claim 6, in which said memory cell includes a first region of the other conductivity type formed in the surface portion of the substrate in contact with said one of source and drain regions of the transfer transistor in said memory cell and in opposition to said conductive layer and a second region of one conductivity type formed in contact with an undersurface of said first region.
Claim 9
Dependent Claim
85 words
A semiconductor memory device according to claim 1, in which the source and drain regions of said driver transistor of said peripheral circuit have a high impurity region and allow impurity region formed in contact with said high impurity region; and said source and drain regions of the transfer transistor in said memory cell are formed by impurity regions having the same impurity concentration as that of the low impurity region of said source and drain regions of said driver transistor of said peripheral circuit.
Claim 10
Dependent Claim
90 words
A semiconductor memory device according to claim 1, in which a capacitor in said memory cell includes an insulating layer formed on a surface of said substrate such that it is situated adjacent one of source and drain regions of said transfer transistor in said memory cell and a conductive layer formed as one plate of the capacitor on the insulating layer to cover a part of said substrate which forms the other plate of said capacitor and which is in contact with said one of source and drain regions.
Claim 11
Dependent Claim
73 words
A semiconductor memory device according to claim 9, in which said memory cell includes a first region of the other conductivity type formed in the surface portion of the substrate in contact with said one of source and drain regions of the transfer transistor in said memory cell and in opposition to said conductive layer and a second region of one conductivity type formed in contact with an undersurface of said first region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |