Semiconductor memory device

Claim 1

A semiconductor substrate of a first conductivity type, having a surface in which intersecting grooves are formed to define a plurality of island portions each of which has sidewalls and a top surface region between said intersecting grooves, said grooves having a bottom surface; and (b) an array of memory cells which are formed in said surface of said substrate, and each of which comprises, (i) a capacitor buried in the grooves surrounding one island layer, and comprising a capacitor electrode layer insulatively provided over a bottom surface of said grooves, and a first semiconductor layer of a second conductivity type formed in a bottom portion of said straight vertical sidewalls so as to face said capacitor electrode layer, and (ii) a transistor comprising a gate electrode layer formed in said grooves so as to be insulatively stacked over said capacitor electrode layer, said gate electrode layer facing a corresponding side surface region of said island portion; wherein the gate electrodes of the transistors of adjacent memory cells are continuously and integrally formed so that gate electrodes of adjacent transistors are in direct contact; wherein said memory cells included in said cell array include two neighboring cells defined by intersecting ones of said grooves, wherein a corner of one of said two neighboring cells is adjacent a corner of the other of said two neighboring cells such that the grooves defining said adjacent corners of said two neighboring cells lie in pair of straight lines crossing at said adjacent corners, the gate electrodes of said two neighboring cells directly contacting each other at said adjacent corners.