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Patent US4990975A successfully refreshed from Google Patents.
US4990975A
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Insulated gate bipolar transistor and method of manufacturing the same
Assignee: Mitsubishi Electric Corp
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Filing: 1989-04-21
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Granted: 1991-02-05
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Expires: 2009-04-21
Abstract
Abstract A P-type base region, which is formed on an N-type body layer, has a relatively deep first base region and a relatively shallow second base region. An N + -type emitter region is formed on the base region. A portion of the surface of the second base region between surfaces of the emitter region and body layer is defined as a channel. A gate oxide film, on which a gate electrode is formed, is provided on the channel. The amount and depth of introduction of an impurity in the second base region is about 2×10 14 to 5×10 14 cm -2 and 4 to 10 μm, respectively. The thickness of the gate oxide film is about 600 to 1000 Å. Thus, an IGBT is implemented, which can ensure sufficient pulse energization ability while causing no latch-up in application to a stroboscope circuit.
Inventors
- 👤 Hiroyasu Hagino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:13
CPC Classifications
H; H10; H10D; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D12/411; H10D12/441; H10D62/00; H10D62/10; H10D62/17; H10D62/393
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
182 words
An insulated gate bipolar transistor comprising: a first conductivity type first semiconductor layer having first and second major surfaces; a second conductivity type second semiconductor layer formed on said first major surface of said first semiconductor layer; a first conductivity type well region formed on said second semiconductor layer, said well region comprising a relatively deep first semiconductor region and a relatively shallow second semiconductor region which are adjacent to each other, said second semiconductor region having an impurity dose amount of about 2×10 14 to 5×10 14 cm -2 and a depth of about 4 to 10 μm; a second conductivity type third semiconductor region formed on said well region; an oxide film formed on a portion of a surface of said send semiconductor region between surfaces of said third semiconductor region and said second semiconductor layer, said oxide film having a thickness of about 600 to 1000 Å; a control electrode formed on said oxide film; a first electrode formed on said third semiconductor region; and a second electrode formed on said second major surface of said first semiconductor layer.
Claim 2
Dependent Claim
182 words
An insulated gate bipolar transistor comprising: a first conductivity type first semiconductor layer having first and second major surfaces; a second conductivity type second semiconductor layer formed on said first major surface of said first semiconductor layer; a first conductivity type well region formed on said second semiconductor layer, said well region comprising a relatively deep first semiconductor region and a relatively shallow second semiconductor region which are adjacent to each other, said second semiconductor region having an impurity dose amount of about 2×10 14 to 5×10 14 cm -2 and a depth of about 4 to 10 μm; a second conductivity type third semiconductor region formed on said well region; an oxide film formed on a portion of a surface of said send semiconductor region between surfaces of said third semiconductor region and said second semiconductor layer, said oxide film having a thickness of about 600 to 1000 Å; a control electrode formed on said oxide film; a first electrode formed on said third semiconductor region; and a second electrode formed on said second major surface of said first semiconductor layer.
Claim 3
Dependent Claim
51 words
An insulated gate bipolar transistor in accordance with claim 1, wherein a portion of said second semiconductor region between said third semiconductor region and said second semiconductor layer is defined as a channel region, a width per unit area of said channel region being more than about 300 cm -1 .
Claim 4
Dependent Claim
47 words
An insulated gate bipolar transistor in accordance with claim I, further comprising a second conductivity type third semiconductor layer formed between said first and second semiconductor layers, a product of average impurity concentration and thickness of said third semiconductor layer being about 10 14 cm -2 .
Claim 5
Dependent Claim
29 words
An insulated gate bipolar transistor in accordance with claim 1, wherein said second semiconductor layer is about 20 to 30 Ω·cm in resistivity and about 50 μm in thickness.
Claim 6
Dependent Claim
24 words
An insulated gate bipolar transistor in accordance with claim 1, wherein said first semiconductor layer has a resistivity of about 0.05 to 0.002 Ω·cm.
Claim 7
Dependent Claim
28 words
An insulated gate bipolar transistor in accordance with claim 1, wherein said first electrode includes an electrode formed both On said third semiconductor region and said well region.
Claim 8
Dependent Claim
54 words
An insulated gate bipolar transistor in accordance with claim 1, further comprising a fourth semiconductor region formed in a center of said well region, said fourth semiconductor region having an impurity dose amount of about 0.8×10 15 to 1×10 15 cm -2 and a depth of about half that of said second semiconductor region.
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