MOS FET semiconductor device having a cell pattern arrangement for optimizing channel width

Claim 2

A semiconductor device comprising a first semiconductor layer having one conductivity type and including a major surface; a first insulating layer applied on the major surface of said first semiconductor layer; a second semiconductor layer having a conductivity type opposite to said one conductivity type, said second semiconductor layer being located within the major surface of said first semiconductor layer and forming a plurality of mutually spaced parallel unit cells each having one of first and second surface patterns, said first pattern consisting of two enlarged portions interconnected by an elongated portion and said second pattern consisting of first, second and third enlarged portions and first and second elongated portions, said first and second enlarged portion being connected to each other by said first elongated portion and said second and third enlarged portions being connected to each other by said second elongated portion, the enlarged and elongated portions of said unit cells being interdigitally arranged on said first semiconductor layer such that the distances between the corners of adjacent obliquely aligned cells are substantially equal to the distances between opposing sides of adjacent cells; a gate electrode film applied on said first insulating layer and having a plurality of openings whose contour configuration corresponds to a pattern of said unit cells, said gate electrode film being formed of a material selected from the group consisting of semiconductive and conductive materials; a third semiconductor layer having said one conductivity type, said third semiconductor layer being formed in the major surface of said first semiconductor layer within said second semiconductor layer, said first insulating film being interposed between said gate electrode film and each of said second and third semiconductor layers; a second insulating layer formed on said gate electrode film and a part of said third semiconductor layer; and a metal electrode film applied on said second insulating layer, said metal electrode film being connected to at least said third semiconductor layer through a plurality of openings formed in said second insulating layer at the enlarged portions of said second semiconductor layer.

Claim 3

A semiconductor device according to claim 1, wherein said enlarged portions are each in the shape of a polygon having an even number of sides.

Claim 4

A semiconductor device according to claim 2, wherein said enlarged portions have a rectangular shape.

Claim 5

A semiconductor device according to claim 2, wherein said enlarged portions have an hexagonal shape.

Claim 6

A semiconductor device according to claim 2, wherein said enlarged portions have an octagonal shape.

Claim 7

A semiconductor device according to claim 5, wherein said metal electrode film is connected to both said second and third semiconductor layers at said enlarged portions.

Claim 8

A semiconductor device according to claim 1, wherein said metal electrode film is connected to said second semiconductor layer at at least one enlarged portion and to said third semiconductor layer at at least one other of said enlarged portions.

Claim 9

A semiconductor device comprising a first semiconductor layer having one conductivity type and including a major surface; a first insulating layer applied on the major surface of said first semiconductor layer; a second semiconductor layer having a conductivity type opposite to said one conductivity type, said second semiconductor layer being located within the major surface of said first semiconductor layer and forming a plurality of mutually spaced parallel unit cells each having at least two enlarged portions and at least one elongated portion interconnecting said enlarged portions, the enlarged and elongated portions of said unit cells being interdigitally arranged in said first semiconductor layer in a pattern such that the distances between the corners of adjacent obliquely aligned cells are substantially equal to the distances between opposing sides of adjacent cells; a gate electrode film applied on said first insulating layer and including a continuous portion having a plurality of openings whose contour configuration corresponds to the pattern of said unit cells and a pluraltiiy of independent portions each situated within the openings of said continuous portion, said gate electrode film being formed of a material selected from the group consisting of semiconductive and conductive materials; a third semiconductor layer having said one conductivity type, said third semiconductor layer being formed in the major surface of said first semiconductor layer within said second semiconductor layer, said first insulating layer being interposed between said gate electrode film and each of said second and third semiconductor layers; a second insulating layer formed on said gate electrode film and a part of said third semiconductor layer; a plurality of first metal electrode films applied on said second insulating layer, said first metal electrode films being connected to at least said third semiconductor layer through a plurality of openings formed in said second insulating layer at the enlarged portions of said second semiconductor layer; and a plurality of second metal electrode films applied on said second insulating layer such that said second metal electrode films are interposed between adjacent first metal electrode films, said second metal electrode films being connected to said continuous portions and independent portions of the gate electrode film through a plurality of openings formed in said second insulating layer.

Claim 10

A semiconductor device comprising a first semiconductor layer having one conductivity type and including a major surface; a first insulating layer applied on the major surface of said first semiconductor layer; a second semiconductor layer having a conductivity type opposite to said one conductivity type, said second semiconductor layer being located within the major surface of said first semiconductor layer and forming a plurality of mutually spaced parallel unit cells each having at least two enlarged portions and at least one elongated portion interconnecting said enlarged portions, the enlarged and elongated portions of said unit cells being interdigitally arranged in said first semiconductor layer in a pattern such that the distances between the corners of adjacent obliquely aligned cells are substantially equal to the distances between opposing sides of adjacent cells; a gate electrode film applied on said first insulating layer and including a continuous portion having a plurality of openings whose contour configuration corresponds to the pattern of said unit cells and a pluraltiiy of independent portions each situated within the openings of said continuous portion, said gate electrode film being formed of a material selected from the group consisting of semiconductive and conductive materials; a third semiconductor layer having said one conductivity type, said third semiconductor layer being formed in the major surface of said first semiconductor layer within said second semiconductor layer, said first insulating layer being interposed between said gate electrode film and each of said second and third semiconductor layers; a second insulating layer formed on said gate electrode film and a part of said third semiconductor layer; a plurality of first metal electrode films applied on said second insulating layer, said first metal electrode films being connected to at least said third semiconductor layer through a plurality of openings formed in said second insulating layer at the enlarged portions of said second semiconductor layer; and a plurality of second metal electrode films applied on said second insulating layer such that said second metal electrode films are interposed between adjacent first metal electrode films, said second metal electrode films being connected to said continuous portions and independent portions of the gate electrode film through a plurality of openings formed in said second insulating layer.

Claim 11

A semiconductor device according to claim 8, wherein a plurality of unit cells each formed by three enlarged portions connected serially by two elongated portions are interdigitally arranged such that the elongated portions extend parallel with each other in a first direction, the distances between adjacent enlarged portions are substantially equal to each other, and the first and second metal electrode films are formed by stripes arranged alternately and extending parallel with each other in a second direction perpendicular to said first direction.

Claim 12

A semiconductor device according to claim 9, wherein each of said independent portions of the gate electrode film is formed in a middle enlarged portion in each of said unit cells.

Claim 13

A semiconductor device according to claim 10, wherein the width of the stripes of the first metal electrode film is wider than the width of the stripes of the second metal electrode film.

Claim 14

A semiconductor device according to claim 10, wherein said middle enlarged portion is larger than the remaining two enlarged portions in the same unit cell.

Claim 15

A semiconductor device according to claim 10, wherein the enlarged portions have a rectangular shape.

Claim 16

A semiconductor device according to claim 10, wherein the enlarged portions have an octagonal shape.

Claim 17

A semiconductor device according to claim 9, wherein said first, second and third semiconductor layers are formed of silicon.

Claim 18

A semiconductor device according to claim 15, wherein said first insulating layer is formed of silicon oxide.

Claim 19

A semiconductor device according to claim 15, wherein said gate electrode film is made of poly-silicon.

Claim 20

A semiconductor device according to claim 15, wherein said gate electrode film is made of a metal selected from the group consisting of Mo, Ni, Ti, Cr and metal silicides, said metals having relatively high melting points.