US4987534A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Processor having synchronized operation between a CPU and a vector processor
Assignee: NEC Corp
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Filing: 1989-07-17
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Granted: 1991-01-22
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Expires: 2009-07-17
Abstract
Abstract A vector processor which maintains synchronization with an associated CPU by limiting the operational instruction proceedings. The vector processor utilizes an instruction register to store instructions from the CPU logical operations circuitry word processing in parallel with the CPU in accordance with instructions from the instruction register and a counter which increases in response to a start instruction from the CPU and decreases in response to the completion of an operation by the logical operation circuitry. A restraining signal is generated in response to a prescribed count of the counter, which delays the execution of the microprogram by the CPU. An indicator device is used for indicating storage of an instruction in the instruction register and a flag device is set in response to a start instruction from the CPU which actuates the indicator means even if no instruction is stored in the instruction register. A decision circuit is utilized to determine in response to a prescribed count of the counter whether or not the execution of the microprogram by the CPU is restrained. If it is determined that the execution is not restrained the decision circuitry actuates the indicator device in response to a start instruction from the CPU without setting the flag device. A start instruction for instructing the start of processing by the logical operation circuitry is generated in response to an indication by the indicator device. A detector circuit is utilized to detect a decrease in the counter and to prevent the execution of a restraining signal.
Inventors
- 👤 Sunao Sekiguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:45
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/38; G06F9/3877; G06F9/3885; G06F9/3887
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
323 words
A processor which processes a sequential series of instructions, said processor comprising: a central processing unit (CPU) processing an N-th instruction, where N represents a position of said N-th instruction in said sequential series of instructions; indicator means, coupled to said CPU and responsive to an instruction load signal from said CPU, for generating a first signal when said indicator means is actuated, said first signal taking a first level when an instruction of said sequential series of instructions is stored into an instruction storage unit which is coupled to said CPU; logical operation means, coupled to said CPU and to said indicator means and responsive to said first signal, for executing a vector operation in accordance with an M-th instruction, in parallel with execution in said CPU, where M represents a position of said M-th instruction in said sequential series of instructions; counter means, coupled to said CPU and to said logical operation means, for indicating a difference between N and M at a given instant in time, said counter means storing a count value which increases in response to a processing start instruction from said CPU and decreases in response to completion of an operation by said logical operation means; flag means, coupled to said CPU and to said indicator means and set in response to said processing start instruction from said CPU, for actuating said indicator means when said flag means is set; and decision means, coupled to said CPU, to said indicator means, to said counter means, and to said flag means, for determining, in accordance with an increase of said count value of said counter means to a prescribed count value in response to said processing start instruction from said CPU, whether or not execution by said CPU is restrained and, if execution is not restrained, actuating said indicator means in response to said processing start instruction from said CPU irregardless of whether said flag means is set.
Claim 2
Dependent Claim
323 words
A processor which processes a sequential series of instructions, said processor comprising: a central processing unit (CPU) processing an N-th instruction, where N represents a position of said N-th instruction in said sequential series of instructions; indicator means, coupled to said CPU and responsive to an instruction load signal from said CPU, for generating a first signal when said indicator means is actuated, said first signal taking a first level when an instruction of said sequential series of instructions is stored into an instruction storage unit which is coupled to said CPU; logical operation means, coupled to said CPU and to said indicator means and responsive to said first signal, for executing a vector operation in accordance with an M-th instruction, in parallel with execution in said CPU, where M represents a position of said M-th instruction in said sequential series of instructions; counter means, coupled to said CPU and to said logical operation means, for indicating a difference between N and M at a given instant in time, said counter means storing a count value which increases in response to a processing start instruction from said CPU and decreases in response to completion of an operation by said logical operation means; flag means, coupled to said CPU and to said indicator means and set in response to said processing start instruction from said CPU, for actuating said indicator means when said flag means is set; and decision means, coupled to said CPU, to said indicator means, to said counter means, and to said flag means, for determining, in accordance with an increase of said count value of said counter means to a prescribed count value in response to said processing start instruction from said CPU, whether or not execution by said CPU is restrained and, if execution is not restrained, actuating said indicator means in response to said processing start instruction from said CPU irregardless of whether said flag means is set.
Claim 3
Dependent Claim
379 words
A processor which processes a sequential series of instructions, said processor comprising: a CPU processing an N-th instruction, where N represents a position of said N-th instruction in said sequential series of instructions; indicator means, coupled to said CPU and responsive to an instruction load signal from said CPU, for generating a first signal when said indicator means is actuated, said first signal taking a first level when an instruction of said sequential series of instructions is stored into an instruction storage unit which is coupled to said CPU; logical operation means, coupled to said CPU and to said indicator means and responsive to said first signal, for executing an operation in accordance with M-th instruction, in parallel with execution in said CPU, where M represents a position of said M-th instruction in said sequential series of instructions; counter means, coupled to said CPU and to said logical operation means, for indicating a difference between N and M at a given instant in time, said counter means storing a count value which increases in response to a processing start instruction from said CPU and decreases in response to completion of an operation by said logical operation means; execution restraining signal generator means, coupled to said CPU and to said counter means and responsive to a prescribed count value of said counter means, for generating a restraining signal for restraining execution of instructions from said sequential series of instructions by said CPU and for transmitting said restraining signal to said CPU; flag means, coupled to said CPU and to said indicator means, and set in response to said processing start instruction from said CPU, for actuating said indicator means when said flag means is set; and detector means, coupled to said indicator means, to said logical operation means, to said counter means, and to said flag means, for detecting, when said flag means is in a set state and said restraining signal has been generated from said execution restraining signal generator means, that a count value of said counter means has decreased wherein generation of said restraining signal from said execution restraining signal generator means is thereafter prevented and for activating said indicator means at a next clock cycle in response to completion of operation of said logical operation means.
Claim 4
Dependent Claim
379 words
A processor which processes a sequential series of instructions, said processor comprising: a CPU processing an N-th instruction, where N represents a position of said N-th instruction in said sequential series of instructions; indicator means, coupled to said CPU and responsive to an instruction load signal from said CPU, for generating a first signal when said indicator means is actuated, said first signal taking a first level when an instruction of said sequential series of instructions is stored into an instruction storage unit which is coupled to said CPU; logical operation means, coupled to said CPU and to said indicator means and responsive to said first signal, for executing an operation in accordance with M-th instruction, in parallel with execution in said CPU, where M represents a position of said M-th instruction in said sequential series of instructions; counter means, coupled to said CPU and to said logical operation means, for indicating a difference between N and M at a given instant in time, said counter means storing a count value which increases in response to a processing start instruction from said CPU and decreases in response to completion of an operation by said logical operation means; execution restraining signal generator means, coupled to said CPU and to said counter means and responsive to a prescribed count value of said counter means, for generating a restraining signal for restraining execution of instructions from said sequential series of instructions by said CPU and for transmitting said restraining signal to said CPU; flag means, coupled to said CPU and to said indicator means, and set in response to said processing start instruction from said CPU, for actuating said indicator means when said flag means is set; and detector means, coupled to said indicator means, to said logical operation means, to said counter means, and to said flag means, for detecting, when said flag means is in a set state and said restraining signal has been generated from said execution restraining signal generator means, that a count value of said counter means has decreased wherein generation of said restraining signal from said execution restraining signal generator means is thereafter prevented and for activating said indicator means at a next clock cycle in response to completion of operation of said logical operation means.
Claim 5
Dependent Claim
483 words
A processor which processes a sequential series of instructions, said processor comprising: a CPU processing an N-th instruction, where N represents a position of said N-th instruction in said sequential series of instructions; indicator means, coupled to said CPU and responsive to an instruction load signal from said CPU, for generating a first signal when said indicator means is actuated, said first signal taking a first level when an instruction of said sequential series of instructions is stored into an instruction storage unit which is coupled to said CPU; logical operation means, coupled to said CPU, for executing an operation in accordance with an M-th instruction, in parallel with execution in said CPU, where M represents a position of said M-th instruction in said sequential series of instructions; counter means, coupled to said CPU and to said logical operation means, for indicating a difference between N and M at a given instant in time, said counter means storing a counter value which increases in response to a processing start instruction from said CPU and decreases in response to completion of an operation by said logical operation means; execution restraining signal generator means, coupled to said CPU and to said counter means and responsive to a prescribed count value of said counter means, for generating a restraining signal for restraining execution of instructions from said sequential series of instructions by said CPU and for transmitting said restraining signal to said CPU; flag means, coupled to said CPU and to said indicator means and set in response to said processing start instruction from said CPU, for actuating said indicator means when said flag means is set; decision means, coupled to said CPU, to said indicator means, to said counter means, and to said flag means, for determining, in accordance with an increase of said count value of said counter means to said prescribed count value in response to said processing start instruction from said CPU, whether or not said execution by CPU is restrained and, if execution is not restrained, actuating said indicator means in response to said processing start instruction from said CPU irregardless of whether said flag means is set; start instruction means, coupled to said indicator means and to said logical operation means and responsive to said first signal, for starting processing by said logical operation means; and detector means, coupled to said indicator means, to said logical operation means, to said counter means, and to said flag means, for detecting, when said flag means is in a set state and said restraining signal has been generated from said execution restraining signal generator means, that a count value of said counter means has decreased, wherein generation of said restraining signal from said execution restraining signal generator means is thereafter prevented and for actuating said indicator means at a next clock cycle in response to completion of operation of said logical operation means.
Claim 6
Dependent Claim
483 words
A processor which processes a sequential series of instructions, said processor comprising: a CPU processing an N-th instruction, where N represents a position of said N-th instruction in said sequential series of instructions; indicator means, coupled to said CPU and responsive to an instruction load signal from said CPU, for generating a first signal when said indicator means is actuated, said first signal taking a first level when an instruction of said sequential series of instructions is stored into an instruction storage unit which is coupled to said CPU; logical operation means, coupled to said CPU, for executing an operation in accordance with an M-th instruction, in parallel with execution in said CPU, where M represents a position of said M-th instruction in said sequential series of instructions; counter means, coupled to said CPU and to said logical operation means, for indicating a difference between N and M at a given instant in time, said counter means storing a counter value which increases in response to a processing start instruction from said CPU and decreases in response to completion of an operation by said logical operation means; execution restraining signal generator means, coupled to said CPU and to said counter means and responsive to a prescribed count value of said counter means, for generating a restraining signal for restraining execution of instructions from said sequential series of instructions by said CPU and for transmitting said restraining signal to said CPU; flag means, coupled to said CPU and to said indicator means and set in response to said processing start instruction from said CPU, for actuating said indicator means when said flag means is set; decision means, coupled to said CPU, to said indicator means, to said counter means, and to said flag means, for determining, in accordance with an increase of said count value of said counter means to said prescribed count value in response to said processing start instruction from said CPU, whether or not said execution by CPU is restrained and, if execution is not restrained, actuating said indicator means in response to said processing start instruction from said CPU irregardless of whether said flag means is set; start instruction means, coupled to said indicator means and to said logical operation means and responsive to said first signal, for starting processing by said logical operation means; and detector means, coupled to said indicator means, to said logical operation means, to said counter means, and to said flag means, for detecting, when said flag means is in a set state and said restraining signal has been generated from said execution restraining signal generator means, that a count value of said counter means has decreased, wherein generation of said restraining signal from said execution restraining signal generator means is thereafter prevented and for actuating said indicator means at a next clock cycle in response to completion of operation of said logical operation means.
Claim 7
Dependent Claim
389 words
A processor which processes a sequential series of instructions, said processor comprising: a CPU processing an N-th instruction, where N represents a position of said N-th instruction in said sequential series of instructions; indicator means, coupled to said CPU and responsive to an instruction load signal from said CPU, for generating a first signal when said indicator means is actuated, said first signal taking a first level when an instruction of said sequential series of instructions is stored into an instruction storage unit which is coupled to said CPU; logical operation means, coupled to said CPU, for executing an operation in accordance with an M-th instruction, in parallel with execution in said CPU, where M represents a position of said M-th instruction in said sequential series of instructions; counter means, coupled to said CPU and to said logical operation means, for indicating a difference between N and M at a given instant in time, said counter means storing a count value which increases in response to a processing start instruction from said CPU and decreases in response to completion of an operation by said logical operation means; execution restraining signal generator means, coupled to said CPU and to said counter means and responsive to a prescribed count value of said counter means, for generating a restraining signal for restraining execution of instructions from said sequential series of instructions by said CPU and for transmitting said restraining signal to said CPU; flag means, coupled to said CPU and to said indicator means and set in response to said processing start instruction from said CPU, for actuating said indicator means when said flag means is set; decision means, coupled to said CPU, to said indicator means, to said counter means, and to said flag means, for determining, in accordance with an increase of said count value of said counter means to said prescribed count value in response to said processing start instruction from said CPU, whether or not execution by said CPU is restrained and, if execution is not restrained, actuating said indicator means in response to said processing start instruction from said CPU irregardless of whether said flag means is set; and start instruction means, coupled to said indicator means and to said logical operation means and responsive to said first signal, for starting processing by said logical operation means.
Claim 8
Dependent Claim
389 words
A processor which processes a sequential series of instructions, said processor comprising: a CPU processing an N-th instruction, where N represents a position of said N-th instruction in said sequential series of instructions; indicator means, coupled to said CPU and responsive to an instruction load signal from said CPU, for generating a first signal when said indicator means is actuated, said first signal taking a first level when an instruction of said sequential series of instructions is stored into an instruction storage unit which is coupled to said CPU; logical operation means, coupled to said CPU, for executing an operation in accordance with an M-th instruction, in parallel with execution in said CPU, where M represents a position of said M-th instruction in said sequential series of instructions; counter means, coupled to said CPU and to said logical operation means, for indicating a difference between N and M at a given instant in time, said counter means storing a count value which increases in response to a processing start instruction from said CPU and decreases in response to completion of an operation by said logical operation means; execution restraining signal generator means, coupled to said CPU and to said counter means and responsive to a prescribed count value of said counter means, for generating a restraining signal for restraining execution of instructions from said sequential series of instructions by said CPU and for transmitting said restraining signal to said CPU; flag means, coupled to said CPU and to said indicator means and set in response to said processing start instruction from said CPU, for actuating said indicator means when said flag means is set; decision means, coupled to said CPU, to said indicator means, to said counter means, and to said flag means, for determining, in accordance with an increase of said count value of said counter means to said prescribed count value in response to said processing start instruction from said CPU, whether or not execution by said CPU is restrained and, if execution is not restrained, actuating said indicator means in response to said processing start instruction from said CPU irregardless of whether said flag means is set; and start instruction means, coupled to said indicator means and to said logical operation means and responsive to said first signal, for starting processing by said logical operation means.
Claim 9
Dependent Claim
399 words
A processor which processes a sequential series of instructions, said processor comprising: a CPU processing an N-th instruction, where N represents a position of said N-th instruction in said sequential series of instructions; indicator means, coupled to said CPU and responsive to an instruction load signal from said CPU, for generating a first signal when said indicator means is actuated, said first signal taking a first level when an instruction of said sequential series of instructions is stored into an instruction storage unit which is coupled to said CPU; logical operation means, coupled to said CPU, for executing an operation in accordance with an M-th instruction, in parallel with execution in said CPU, where M represents a position of said M-th instruction in said sequential series of instructions; counter means, coupled to said CPU and to said logical operation means, for indicating a difference between N and M at a given instant in time, said counter means storing a count value which increases in response to a processing start instruction from said CPU and decreases in response to completion of an operation by said logical operation means; execution restraining signal generator means, coupled to said CPU and to said counter means and responsive to a prescribed count value of said counter means, for generating a restraining signal for restraining execution of instructions from said sequential series of instructions by said CPU and for transmitting said restraining signal to said CPU; flag means, coupled to said CPU and to said indicator means and set in response to said processing start instruction from said CPU, for actuating said indicator means when said flag means is set; start instruction means, coupled to said indicator means and to said logical operation means and responsive to said first signal, for starting processing by said logical operation means; and detector means, coupled to said indicator means, to said logical operation means, to said counter means, and to said flag means, for detecting, when said flag means is in a set state and said restraining signal has been generated from said execution restraining signal generator means, that a count value of said counter means has decreased, wherein generation of said restraining signal from said execution restraining signal generator means is thereafter prevented and for actuating indicator means is actuated at a next clock cycle in a response to completion of operation by said logical operation means.
Claim 10
Dependent Claim
399 words
A processor which processes a sequential series of instructions, said processor comprising: a CPU processing an N-th instruction, where N represents a position of said N-th instruction in said sequential series of instructions; indicator means, coupled to said CPU and responsive to an instruction load signal from said CPU, for generating a first signal when said indicator means is actuated, said first signal taking a first level when an instruction of said sequential series of instructions is stored into an instruction storage unit which is coupled to said CPU; logical operation means, coupled to said CPU, for executing an operation in accordance with an M-th instruction, in parallel with execution in said CPU, where M represents a position of said M-th instruction in said sequential series of instructions; counter means, coupled to said CPU and to said logical operation means, for indicating a difference between N and M at a given instant in time, said counter means storing a count value which increases in response to a processing start instruction from said CPU and decreases in response to completion of an operation by said logical operation means; execution restraining signal generator means, coupled to said CPU and to said counter means and responsive to a prescribed count value of said counter means, for generating a restraining signal for restraining execution of instructions from said sequential series of instructions by said CPU and for transmitting said restraining signal to said CPU; flag means, coupled to said CPU and to said indicator means and set in response to said processing start instruction from said CPU, for actuating said indicator means when said flag means is set; start instruction means, coupled to said indicator means and to said logical operation means and responsive to said first signal, for starting processing by said logical operation means; and detector means, coupled to said indicator means, to said logical operation means, to said counter means, and to said flag means, for detecting, when said flag means is in a set state and said restraining signal has been generated from said execution restraining signal generator means, that a count value of said counter means has decreased, wherein generation of said restraining signal from said execution restraining signal generator means is thereafter prevented and for actuating indicator means is actuated at a next clock cycle in a response to completion of operation by said logical operation means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-21 | 1994-07-23 | 1995-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-21 | 1998-07-23 | 1999-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-21 | 2002-07-23 | 2003-01-22 | $7700.00 | Window Closed / Lapsed |