Patent US3860503A successfully refreshed from Google Patents.
Patent US4987326A successfully refreshed from Google Patents.
US4987326A
Expired / Lapsed
US
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Semiconductor integrated circuit device having an improved common wiring arrangement
Assignee: Hitachi Ltd
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Filing: 1989-04-28
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Granted: 1991-01-22
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Expires: 2009-04-28
Abstract
Abstract In a gate array integrated circuit including a plurality of logic gate circuits having a wired-OR form, or the like, a first common combined wiring is provided for connecting the output side in such a manner that the output terminal of each logic gate circuit and a branch node corresponding thereto are in the proximity of one another. A terminal resistor is interposed between a first end of the first common combined wiring and a power source voltage or ground potential of the circuit, and the second end of the first common combined wiring is coupled to a second common combined wiring connecting the input terminals of the logic gate circuits on the input side.
Inventors
- 👤 Yasuo Satoh
- 👤 Tohru Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:50
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H10; H10D; H10D84/00; H10D84/90; H10D84/901; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
175 words
A semiconductor integrated circuit device comprising: a first logic gate cell group; a first common wiring for connecting an output terminal of each logic gate cell in said first logic gate cell group in order to connect said output terminals with one another, wherein said first common wiring has a first end and a second end, and wherein said output terminals of each of said logic gate cells in said first logic gate cell are coupled to said first common wiring between said first and said second ends; a terminal resistor disposed inside a logic gate cell connected to the first end of said first common wiring, for setting the output level used commonly for said logic gate cells in said first logic gate cell group; a second logic gate cell group; and a second common wiring coupled to said second end of said first common wiring for connecting an input terminal of each of said logic gate cells in said second logic gate cell group to the second end of said first common wiring.
Claim 2
Dependent Claim
175 words
A semiconductor integrated circuit device comprising: a first logic gate cell group; a first common wiring for connecting an output terminal of each logic gate cell in said first logic gate cell group in order to connect said output terminals with one another, wherein said first common wiring has a first end and a second end, and wherein said output terminals of each of said logic gate cells in said first logic gate cell are coupled to said first common wiring between said first and said second ends; a terminal resistor disposed inside a logic gate cell connected to the first end of said first common wiring, for setting the output level used commonly for said logic gate cells in said first logic gate cell group; a second logic gate cell group; and a second common wiring coupled to said second end of said first common wiring for connecting an input terminal of each of said logic gate cells in said second logic gate cell group to the second end of said first common wiring.
Claim 3
Dependent Claim
40 words
A semiconductor integrated circuit device according to claim 1, wherein each of said logic gate cells includes an emitter coupled logic circuit and an emitter output transistor whose emitter is connected to the output terminal of said logic gate cell.
Claim 4
Dependent Claim
71 words
A semiconductor integrated circuit device according to claim 2, wherein said terminal resistor is connected as an emitter resistor to said emitter output transistor of said logic gate cell connected to the first end of said first common wiring among said logic gate cells of said first logic gate cell group, and said emitter output transistors of the other of said logic gate cells are of an open emitter type. PG,43
Claim 5
Dependent Claim
54 words
A semiconductor integrated circuit device according to claim 3, wherein said semiconductor integrated circuit device is a gate array integrated circuit device and said first and second common wirings are coupled to each other through a logic gate cell connected between said first logic gate cell group and said second logic gate cell group.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-21 | 1994-07-23 | 1995-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-21 | 1998-07-23 | 1999-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-21 | 2002-07-23 | 2003-01-22 | $7700.00 | Window Closed / Lapsed |