US4987091A
Expired / Lapsed
US
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Process of fabricating dynamic random access memory cell
Assignee: NEC Corp
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Filing: 1990-01-22
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Granted: 1991-01-22
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Expires: 2010-01-22
Abstract
Abstract For making an inter-level insulating film between a capacitor electrode and a gate electrode mild at the shoulder portion thereof, a doped polysilicon film is overlain by a silicon oxide film on a dielectric film structure, and the silicon oxide film is slightly etched through an isotropical technique by using a mask layer for forming a hollow space with a generally quarter-circle configuration beneath the mask layer, then anisotropically etching the silicon oxide and the doped polysilicon by using the same mask layer, then depositing silicon oxide on the entire surface, then exposing the surface of a semiconductor substrate by using an etch-back technique for leaving the inter-level insulating film on the capacitor electrode, then forming a gate electrode on the inter-level insulating film. Since a declining shoulder portion takes place at the upper end of the silicon oxide film due to the isotropical etching, the inter-level insulating film and, accordingly, the gate electrode smoothly extend over the capacitor electrode, and, for this reason, the gate electrode is free from undesirable disconnection.
Inventors
- 👤 Hiroshi Kotaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 07:27
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10D; H10D1/00; H10D1/01; H10D1/045; H10D1/047; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P50/00; H10P50/73
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
349 words
A process of fabricating a random access memory cell having a storage capacitor and a switching transistor, comprising the steps of: (a) preparing an oxidizable semiconductor substrate having a capacitor forming portion; (b) forming a dielectric film of said storage capacitor covering at least said capacitor forming portion and a transistor forming area of said oxidizable semiconductor substrate; (c) forming a multiple-level structure having a first oxidizable conductive film on said dielectric film and a first insulating film on the first oxidizable conductive film, said multiple-level structure being provided on the entire structure; (d) providing a first mask layer on said multiple-level structure and located over a capacitor electrode forming area; (e) removing a surface portion of said first insulating film so that a hollow space extends beneath said first mask layer; (f) removing said first insulating film and said first oxidizable conductive film by using said first mask layer, said hollow space causing a declining shoulder portion to take place at an upper edge of said first insulating film; (g) removing said first mask layer; (h) removing said dielectric film from said transistor forming area so that a surface of said oxidizable semiconductor substrate is exposed; (i) oxidizing said first oxidizable conductive film and said oxidizable semiconductor substrate for increasing the thickness of said first insulating film and for forming a second insulating film covering said transistor forming area; (j) depositing a third insulating film on said first and second insulating films; (k) removing a part of said third insulating film and said second insulating film by subjecting an anisotropic etching technique thereto for etching predominately in the vertical direction so that the surface of said oxidizable semiconductor substrate is exposed again, said third insulating film having a declining shoulder portion extending from an upper surface thereof to the surface of said oxidizable semiconductor substrate; (l) growing a gate oxide of said switching transistor on the surface of said oxidizable semiconductor substrate; (m) depositing a second conductive film on the entire surface; and (n) patterning said second conductive film to form a gate electrode of said switching transistor.
Claim 2
Dependent Claim
349 words
A process of fabricating a random access memory cell having a storage capacitor and a switching transistor, comprising the steps of: (a) preparing an oxidizable semiconductor substrate having a capacitor forming portion; (b) forming a dielectric film of said storage capacitor covering at least said capacitor forming portion and a transistor forming area of said oxidizable semiconductor substrate; (c) forming a multiple-level structure having a first oxidizable conductive film on said dielectric film and a first insulating film on the first oxidizable conductive film, said multiple-level structure being provided on the entire structure; (d) providing a first mask layer on said multiple-level structure and located over a capacitor electrode forming area; (e) removing a surface portion of said first insulating film so that a hollow space extends beneath said first mask layer; (f) removing said first insulating film and said first oxidizable conductive film by using said first mask layer, said hollow space causing a declining shoulder portion to take place at an upper edge of said first insulating film; (g) removing said first mask layer; (h) removing said dielectric film from said transistor forming area so that a surface of said oxidizable semiconductor substrate is exposed; (i) oxidizing said first oxidizable conductive film and said oxidizable semiconductor substrate for increasing the thickness of said first insulating film and for forming a second insulating film covering said transistor forming area; (j) depositing a third insulating film on said first and second insulating films; (k) removing a part of said third insulating film and said second insulating film by subjecting an anisotropic etching technique thereto for etching predominately in the vertical direction so that the surface of said oxidizable semiconductor substrate is exposed again, said third insulating film having a declining shoulder portion extending from an upper surface thereof to the surface of said oxidizable semiconductor substrate; (l) growing a gate oxide of said switching transistor on the surface of said oxidizable semiconductor substrate; (m) depositing a second conductive film on the entire surface; and (n) patterning said second conductive film to form a gate electrode of said switching transistor.
Claim 3
Dependent Claim
26 words
A process of fabricating a dynamic random access memory cell as set forth in claim 1, in which said oxidizable semiconductor substrate is formed of silicon.
Claim 4
Dependent Claim
32 words
A process of fabricating a dynamic random access memory cell as set forth in claim 2, in which said capacitor forming portion occupies a flat surface portion of said oxidizable semiconductor substrate.
Claim 5
Dependent Claim
28 words
A process of fabricating a dynamic random access memory cell as set forth in claim 3, in which a lower electrode is formed in said capacitor forming portion.
Claim 6
Dependent Claim
32 words
A process of fabricating a dynamic random access memory cell as set forth in claim 4, in which said dielectric film is formed by a silicon nitride sandwiched between silicon oxide films.
Claim 7
Dependent Claim
26 words
A process of fabricating a dynamic random access memory cell as set forth in claim 5, in which conductive film is formed by a doped polysilicon.
Claim 8
Dependent Claim
28 words
A process of fabricating a dynamic random access memory cell as set forth in claim 6, in which said first insulating film is formed by a silicon oxide.
Claim 9
Dependent Claim
37 words
A process of fabricating a dynamic random access memory cell as set forth in claim 7, in which said step (e) is a achieved by using an isotropical etching technique so as to form said hollow space.
Claim 10
Dependent Claim
29 words
A process of fabricating a dynamic random access memory cell as set forth in claim 8, in which said step (f) is achieved by using an anisotropical etching technique.
Claim 11
Dependent Claim
33 words
A process of fabricating a dynamic random access memory cell as set forth in claim 8, in which said isotropical etching is carried out by using an etchant of a buffered fluoric acid.
Claim 12
Dependent Claim
28 words
A process of fabricating a dynamic random access memory cell as set forth in claim 10, in which said third insulating film is formed of a silicon oxide.
Claim 13
Dependent Claim
27 words
A process of fabricating a dynamic random access memory cell as set forth in claim 11, in which said second conductive film is formed of a polysilicon.
Claim 14
Dependent Claim
59 words
A process of fabricating a dynamic random access memory cell as set forth in claim 12, in which said process further comprises the steps of (o) selectively doping impurity atoms into the surface of said oxidizable semiconductor substrate so as to form a source of said switching transistor; and (p) covering the entire surface with a fourth insulating film.
Claim 15
Dependent Claim
55 words
A process of fabricating a dynamic random access memory cell as set forth in claim 1, in which said step (a) comprises sub-steps of (a-1) forming a trench in said oxidizable semiconductor substrate, said trench being defined by a wall portion of said oxidizable semiconductor substrate, and (a-2) doping said wall portion with impurity atoms.
Claim 16
Dependent Claim
34 words
A process of fabricating a dynamic random access memory cell as set forth in claim 14, in which said dielectric film comprises a triple level structure having a nitride film sandwiched between oxide films.
Claim 17
Dependent Claim
27 words
A process of fabricating a dynamic random access memory cell as set forth in claim 15, in which said oxidizable semiconductor substrate is formed of a silicon.
Claim 18
Dependent Claim
37 words
A process of fabricating a dynamic random access memory cell as set forth in claim 16, in which said nitride film is of a silicon nitride, and in which said oxide films are of a silicon oxide.
Claim 19
Dependent Claim
38 words
A process of fabricating a dynamic random access memory cell as set forth in claim 13, in which said gate electrode of said switching transistor is partially overlapped with the remaining portion of said oxidizable first conductive film.
Claim 20
Dependent Claim
38 words
A process of fabricating a dynamic random access memory cell as set forth in claim 17, in which said gate electrode of said switching transistor is partially overlapped with the remaining portion of said oxidizable first conductive film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-01-21 | 1994-07-23 | 1995-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-21 | 1998-07-23 | 1999-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-21 | 2002-07-23 | 2003-01-22 | $7700.00 | Window Closed / Lapsed |