Dynamic random access memory device having a plurality of one transistor type memory cells

Claim 2

A dynamic random access memory device comprising a semiconductor substrate of one conductivity type and having a major surface, a transfer gate transistor formed on said major surface of said substrate and having source and drain regions of a conductivity type opposite to said substrate, a trench formed in said substrate from said major surface of said substrate into said substrate, said trench having an upper wall adjacent to said major surface of said substrate and a lower wall adjacent to said upper wall continuously and including a bottom portion, an impurity layer of a conductivity type opposite to said substrate formed on said upper and lower walls of said trench and connected to one of said source and drain regions of said transistor, a dielectric film of a storage capacitor, said dielectric film including a first portion provided on said upper wall of said trench and a second portion provided on said lower wall of said trench, said first portion of said dielectric film being thicker than said second portion of said dielectric film, and a capacitor electrode continuously formed on said first and second portions of said dielectric film within said trench.

Claim 3

A memory device of claim 1, in which the depth of said upper wall of said trench from said major surface of said substrate ranges from 0.5 μm to 2.0 μm.

Claim 4

A memory device of claim 1, in which said dielectric film of said capacitor includes a first silicon oxide film on said upper and lower walls of said trench with a substantially uniform thickness and a silicon nitride film on the surface of said first silicon oxide film, the thickness of said silicon nitride film on said upper wall of said trench being larger than the thickness of said silicon nitride film on said lower wall of said trench.

Claim 5

A memory device of claim 3, in which said dielectric film of said capacitor further includes a second silicon oxide film on the surface of said silicon nitride film on said upper and lower walls of said trench with a substantially uniform thickness, whereby said first portion of said dielectric film is constituted by said first silicon oxide film, said thick silicon nitride film and said second silicon oxide film, and said second portion of said dielectric film is constituted by said first silicon oxide film, said thin silicon nitride film and said second silicon oxide film

Claim 6

A memory device of claim 3, in which said thickness of said silicon nitride film on said upper wall is 1.5 times or more and 3.0 times or less said thickness of said silicon nitride film on said lower wall of said trench.

Claim 7

A memory device of claim 4, in which said first and second silicon oxide films are thermally grown films, and said silicon nitride film is a chemically vapour deposited film.

Claim 8

A memory device of claim 4, in which the thickness of said second silicon oxide film ranges from 2 nm to 6 nm.

Claim 9

A memory device of claim 1, in which said dielectric film is constituted only by a thermally grown silicon oxide film.

Claim 10

A memory device of claim 1 further comprising an impurity region of said one conductivity type and having a higher impurity concentration than that of said substrate, said impurity region surrounding said impurity layer.

Claim 11

A dynamic random access memory device comprising a semiconductor substrate of one conductivity type and having a major surface, a transfer gate transistor formed on said major surface of said substrate and having source and drain regions of a conductivity type opposite to said substrate, a trench formed in said substrate from said major surface of said substrate into said substrate, said trench having an upper wall adjacent to said major surface of said substrate and a lower wall adjacent to said upper wall continuously and including a bottom portion, a dielectric film of a storage capacitor, said dielectric film including a first portion provided on said upper wall of said trench and a second portion provided on said lower wall of said trench, said first portion of said dielectric film being thicker than said second portion of said dielectric film, a capacitor electrode continuously formed on said first and second portions of said dielectric films within said trench, and an inversion layer of a conductivity type opposite to said substrate formed on said upper and lower walls of said trench and connected to one of said source and drain regions of said transistor, said inversion layer being produced when a voltage is applied to said capacitor electrode.

Claim 12

A dynamic random access memory device comprising a semiconductor substrate of one conductivity type and having a major surface, a transfer gate transistor formed on said major surface of said substrate and having source and drain regions of a conductivity type opposite to said substrate, a trench formed in said substrate from said major surface of said substrate into said substrate, said trench having an upper wall adjacent to said major surface of said substrate and a lower wall adjacent to said upper wall continuously and including a bottom portion, a dielectric film of a storage capacitor, said dielectric film including a first portion provided on said upper wall of said trench and a second portion provided on said lower wall of said trench, said first portion of said dielectric film being thicker than said second portion of said dielectric film, a capacitor electrode continuously formed on said first and second portions of said dielectric films within said trench, and an inversion layer of a conductivity type opposite to said substrate formed on said upper and lower walls of said trench and connected to one of said source and drain regions of said transistor, said inversion layer being produced when a voltage is applied to said capacitor electrode.