Semiconductor memory circuit

Claim 2

A semiconductor memory circuit capable of changing the numbers of bits and words associated therewith, the circuit comprising: chip control means for at least selecting a bit construction corresponding to the number of bits per word and for switching between a random access memory function and a first-in first-out memory function; an address buffer for altering an effective address length on the basis of the selected bit construction; an address counter for counting up a write address or a read address in each write or read operation when the first-in first-out memory function has been selected; a memory cell array; column and line decoders each for controlling said memory cell array on the basis of the selected bit construction; and an input/output for changing an effective data length on the basis of the selected bit construction.

Claim 3

A circuit according to claim 1 wherein the write and read operations are independently executable when the first-in first-out memory function has been selected.

Claim 4

A circuit according to claim 1 wherein it is programmable whether the memory circuit itself is to be used or not.

Claim 5

A circuit according to claim 1 wherein it further comprises an input/output selection switch for enabling at least part of an input of said address buffer, and inputs and outputs of said input/output buffer to be selected.

Claim 6

A circuit according to claim 1 wherein said chip control means monitors counted values by said address counter, and issues an alarm signal when an address for which no information has been written is assigned for read out.

Claim 7

A semiconductor memory circuit capable of changing the number of bits and words associated therewith, the circuit comprising: timing control means at least for selecting a bit construction corresponding to the number of bits per word and for switching between a random access memory function and a first-in first-out memory function; an address buffer for changing an effective address length based on the selected bit construction; a write address counter and a read address counter separate from said write address counter for independenty counting up write and read addresses each write and read operation when the first-in first-out memory function has been selected; write address switching means for making valid an address input from said address buffer when the random access memory function has been selected, while making valid an address input from said write address counter when the first-in first-out memory function has been selected; read address switching means for making valid an address input from said address buffer when the random access memory function has been selected, while making valid an address input from said read address counter when the first-in first-out memory function has been selected; an input buffer and an output buffer separate from said input buffer, said input and output buffers cooperatively having a function to change an effective data length based upon the selected bit construction; a memory cell array; write column and line decoders for controlling said memory cell array based upon the selected bit construction; and read column and line decoders for controlling said memory cell array based upon the selected bit construction.

Claim 8

A semiconductor memory circuit capable of changing the number of bits and words associated therewith, the circuit comprising: timing control means at least for selecting a bit construction corresponding to the number of bits per word and for switching between a random access memory function and a first-in first-out memory function; an address buffer for changing an effective address length based on the selected bit construction; a write address counter and a read address counter separate from said write address counter for independenty counting up write and read addresses each write and read operation when the first-in first-out memory function has been selected; write address switching means for making valid an address input from said address buffer when the random access memory function has been selected, while making valid an address input from said write address counter when the first-in first-out memory function has been selected; read address switching means for making valid an address input from said address buffer when the random access memory function has been selected, while making valid an address input from said read address counter when the first-in first-out memory function has been selected; an input buffer and an output buffer separate from said input buffer, said input and output buffers cooperatively having a function to change an effective data length based upon the selected bit construction; a memory cell array; write column and line decoders for controlling said memory cell array based upon the selected bit construction; and read column and line decoders for controlling said memory cell array based upon the selected bit construction.

Claim 9

A circuit according to claim 6 wherein said memory cell array comprises a plurality of memory cells interconnected by bit lines and word lines, and each memory cell of said memory cell array is a static random access memory comprising inverters for holding information, and selection transistors for connecting and disconnecting each memory cell to and from the associated bit lines in conformity with signal levels on the associated word lines, and separate word lines and bit lines are provided for write and read operations.

Claim 10

A circuit according to claim 6 wherein when the write address and the read address are coincident with each other, a write operation has priority to be executed.

Claim 11

A circuit according to claim 6 wherein the write operation is interrupted when the write address counter contains a maximum count at the time of the write operation, and the write operation is restarted from the oldest address when a write reset signal is entered.