Speed enhancement technique for CMOS circuits

Claim 2

A circuit comprising: a plurality of cascaded stages, each stage capable of being placed in one of a first logic state or a second logic state, wherein the first logic state of at least one selected stage is controlled by at least one stage immediately preceding the selected stage, while the second logic state is primarily controlled by at least one stage following the selected stage.

Claim 3

A circuit as in claim 1 wherein the circuit further includes a first and a second potential source, and each stage comprises: an input node; an output node; first switching means connected to the input node, the output node, and to one of the first and second potential sources for connecting the output node to one of the first and second potential sources in response to a first type signal on the input node; and second switching means connected to the output node, to the other of the first and second potential sources, and to said following stage, for connecting the output node to the other of the first and second potential sources in delayed response to the earlier first type signal on the input node.

Claim 4

A circuit as in claim 2 wherein: the first potential source is higher than the second potential source; and the first switching means and the second switching means comprise first and second transistors, respectively.

Claim 5

A circuit as in claim 3 wherein: the first transistor has a gate connected to the input node, a source connected to the second potential source, and a drain connected to the output node; and the second transistor has a gate connected to an output node of the following stage, a drain connected to the output node, and a source connected to the first potential source.

Claim 6

A circuit as in claim 4 wherein: the first transistor is an NMOS transistor; and the second transistor is a PMOS transistor.

Claim 7

A circuit as in claim 3 wherein: the first transistor has a gate connected to the input node, a source connected to the first potential source, and a drain connected to the output node; and the second transistor has a gate connected to an output node of the following stage, a drain connected to the output node, and a source connected to the second potential source.

Claim 8

A circuit as in claim 6 wherein: the first transistor is a PMOS transistor; and the second transistor is an NMOS transistor.

Claim 9

A circuit as in claim 2 wherein each stage further comprises: third switching means connected to the output node, to the other of the first and second potential sources and to the input node for connecting the output node to the other of the first and second potential in response to a second type signal on the input node.

Claim 10

A circuit as in claim 8 wherein: the third switching means comprises a third transistor having a source connected to the other of the first and second potential sources, a drain connected to the output node, and a gate connected to the input node.

Claim 11

A circuit as in claim 9 wherein: the third switching means and the first switching means are complementary type transistors.

Claim 12

A circuit as in claim 10 wherein each of the first, second and third switching means comprise field effect transistors.

Claim 13

A circuit as in claim 2 wherein the input node of the selected stage is connected to the output node of the stage immediately preceding the selected stage.

Claim 14

A circuit as in claim 1 wherein the at least one stage following the selected stage is an even number of stages after the selected stage.

Claim 15

A circuit as in claim 13 wherein the even number is four.

Claim 16

A circuit as in claim 2 wherein: the first switching means comprises a field effect transistor of first channel type; and the second switching means comprises a field effect transistor of complementary type to the first channel type.

Claim 17

A circuit as in claim 15 wherein each stage further comprises: third switching means connected to the output node, to the other of the first and second potential sources and to the input node for connecting the output node to the other of the first and second potential in response to a second type signal on the input node; and the third switching means comprises a field effect transistor of the same channel type as the second switching means.

Claim 18

A circuit as in claim 16 wherein the channel type of the first switching means of the selected stage is opposite the channel type of the first switching means of the immediately preceding stage.

Claim 19

A circuit comprising: a node; logic means coupled to the node independent of the prior state of the node for placing the node in an active logic state at a first time; resetting means coupled to the node and responsive to the active logic state of the node at the first time for changing the logic state of the node to the inactive state at a second time after the first time in response to the active logic state of the node at the first time.

Claim 20

A circuit comprising: a node; logic means coupled to the node independent of the prior state of the node for placing the node in an active logic state at a first time; resetting means coupled to the node and responsive to the active logic state of the node at the first time for changing the logic state of the node to the inactive state at a second time after the first time in response to the active logic state of the node at the first time.

Claim 21

A circuit as in claim 18 wherein the resetting means comprises: a plurality of serially-connected inverters, a first one of which is connected to receive signals supplied by the node; and a resetting circuit connected between the node and a source of signals representative of a desired reset level for the node, the resetting circuit being controlled by a later one of the inverters.

Claim 22

A circuit as in claim 19 wherein the resetting circuit comprises a field effect transistor having a gate connected to the later inverter, a source connected to the source of signals, and a drain connected to the node.

Claim 23

A circuit as in claim 20 wherein each inverter comprises: an input node; an output node; an upper potential; a lower potential; a PMOS transistor having a gate connected to the input node, a source connected to the upper potential, and a drain connected to the output node; an NMOS transistor having a gate connected to the input node, a source connected to the lower potential, and a drain connected to the output node.

Claim 24

A circuit as in claim 19 wherein the plurality of inverters is an even integer.

Claim 25

A circuit as in claim 22 wherein the plurality is four.

Claim 26

A circuit comprising: a high reference potential; a low reference potential; a plurality of serially connected stages; odd numbered stages including: a first input node; a first output node; a first switch connected between the first output node and the high reference potential for connecting the first output node to the high reference potential under control of the first input node; a second switch connected between the first output node and the low reference potential for connecting the first output node to the low reference potential under control of an output node of a stage subsequent to that stage; even numbered stages including: a second input node; a second output node; a first switch connected between the second output node and the low reference potential for connecting the second output node to the low reference potential under control of the second input node; a second switch connected between the second output node and the high reference potential for connecting the second output node to the high reference potential under control of an output node of a stage subsequent to that stage; and wherein the first output node of each odd-numbered stage is connected to the second input node of the next sequential even-numbered stage, and the second output node of each even-numbered stage is connected to the first input node of the next sequential odd-numbered stage.

Claim 27

A circuit comprising: a high reference potential; a low reference potential; a plurality of serially connected stages; odd numbered stages including: a first input node; a first output node; a first switch connected between the first output node and the high reference potential for connecting the first output node to the high reference potential under control of the first input node; a second switch connected between the first output node and the low reference potential for connecting the first output node to the low reference potential under control of an output node of a stage subsequent to that stage; even numbered stages including: a second input node; a second output node; a first switch connected between the second output node and the low reference potential for connecting the second output node to the low reference potential under control of the second input node; a second switch connected between the second output node and the high reference potential for connecting the second output node to the high reference potential under control of an output node of a stage subsequent to that stage; and wherein the first output node of each odd-numbered stage is connected to the second input node of the next sequential even-numbered stage, and the second output node of each even-numbered stage is connected to the first input node of the next sequential odd-numbered stage.

Claim 28

The circuit of claim 24 in which the first switch in said odd-numbered stages consists of at least one PMOS transistor, and in which the first switch in said even-numbered stages consists of at least one NMOS transistor.

Claim 29

The circuit of claim 24 in which the second switch in said odd-numbered stages consists of at least one NMOS transistor, and in which the second switch in said even-numbered stages consists of at least one PMOS transistor.

Claim 30

A circuit comprising: a selected logic stage capable of being placed in one of a first and a second logic state; at least one preceding logic stage coupled to the selected logic stage for controlling the first logic state; and at least one following logic stage coupled to the selected logic stage for controlling the second logic state.

Claim 31

A circuit comprising: a selected logic stage capable of being placed in one of a first and a second logic state; at least one preceding logic stage coupled to the selected logic stage for controlling the first logic state; and at least one following logic stage coupled to the selected logic stage for controlling the second logic state.

Claim 34

A method as in claim 28 wherein the step of using the change comprises: propagating the pulse through delay means to the reset circuit.