Patent US4984036A successfully refreshed from Google Patents.
US4984036A
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Field effect transistor with multiple grooves
Assignee: Mitsubishi Electric Corp
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Filing: 1989-06-19
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Granted: 1991-01-08
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Expires: 2009-06-19
Abstract
Abstract A field effect transistor has an active layer containing a multi-step recess that becomes narrower as it approaches the substrate. A gate electrode is produced at the deepest portion of the recess section. The transistor may be produced by successively selectively etching the active layer and an overlying semiconductor surface protection film to produce a multi-step configuration recess, depositing a gate electrode at the bottom of the recess, and depositing source and drain electrodes on the active layer.
Inventors
- 👤 Shinichi Sakamoto
- 👤 Takuji Sonoda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:48
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10D30/80; H10D30/87; H10D30/877; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
101 words
A transistor including a semiconductor substrate, a doped, active semiconductor layer supported by said semiconductor substrate, a source electrode, a gate electrode, and a drain electrode disposed on said active semiconductor layer, said gate electrode being disposed between said source and drain electrodes for controlling current flow through said active layer between said source and drain electrodes, said active layer including a recess configuration including at least three steps that becomes narrower at each step as the recess approaches said substrate, wherein said gate electrode is disposed on said active layer in the portion of the recess closest to said substrate.
Claim 2
Dependent Claim
101 words
A transistor including a semiconductor substrate, a doped, active semiconductor layer supported by said semiconductor substrate, a source electrode, a gate electrode, and a drain electrode disposed on said active semiconductor layer, said gate electrode being disposed between said source and drain electrodes for controlling current flow through said active layer between said source and drain electrodes, said active layer including a recess configuration including at least three steps that becomes narrower at each step as the recess approaches said substrate, wherein said gate electrode is disposed on said active layer in the portion of the recess closest to said substrate.
Claim 3
Dependent Claim
11 words
The transistor of claim 1 wherein said substrate is semi-insulating GaAs.
Claim 4
Dependent Claim
24 words
The transistor of claim 1 including an undoped semiconductor buffer layer interposed between said substrate and said active layer adjacent to said active layer.
Claim 5
Dependent Claim
31 words
The transistor of claim 3 wherein said active semiconductor layer and said semiconductor buffer layer comprise different semiconductors, thereby forming a heterojunction, whereby said transistor is a high electron mobility transistor.
Claim 6
Dependent Claim
17 words
The transistor of claim 1 wherein said gate electrode forms a Schottky barrier with said active layer.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-07 | 1994-07-09 | 1995-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-07 | 1998-07-09 | 1999-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-07 | 2002-07-09 | 2003-01-08 | $7700.00 | Window Closed / Lapsed |