Abstract A reverse staggered type silicon thin film transistor includes a substrate having a gate electrode; a gate insulating layer on the substrate and the gate electrode, the gate insulating layer having a transistor-forming portion; a lower layer silicon film on the transistor-forming portion of the gate insulating layer and in contact therewith, the lower layer silicon film being formed at a first temperature and with a first thickness; an upper layer silicon film formed on the transistor-forming portion of the gate insulating layer at a second temperature which is lower than the first temperature and with a second thickness greater than the first thickness; and n-type silicon layer on the upper layer silicon film and in contact therewith; a source electrode on the n-type silicon layer; and a drain electrode on the n-type silicon layer.
A reverse staggered type silicon thin film transistor, comprising: a gate electrode on a substrate; a gate insulating layer on said substrate and said gate electrode, said gate insulating layer having a transistor-forming portion; a lower layer silicon film on the transistor-forming portion of the gate insulating layer and in contact therewith, said lower layer silicon film being formed at a first temperature; an upper layer silicon film formed on said lower layer silicon film at a second temperature which is lower than said first temperature, said lower layer silicon film having a first thickness of approximately 30 nm and said upper layer silicon film having a second greater thickness of approximately 120 nm; an n-type silicon layer on said upper layer silicon film and in contact therewith; a source electrode on said n-type silicon layer; and a drain electrode on said n-type silicon layer.
Claim 2
Dependent Claim
145 words
A reverse staggered type silicon thin film transistor, comprising: a gate electrode on a substrate; a gate insulating layer on said substrate and said gate electrode, said gate insulating layer having a transistor-forming portion; a lower layer silicon film on the transistor-forming portion of the gate insulating layer and in contact therewith, said lower layer silicon film being formed at a first temperature; an upper layer silicon film formed on said lower layer silicon film at a second temperature which is lower than said first temperature, said lower layer silicon film having a first thickness of approximately 30 nm and said upper layer silicon film having a second greater thickness of approximately 120 nm; an n-type silicon layer on said upper layer silicon film and in contact therewith; a source electrode on said n-type silicon layer; and a drain electrode on said n-type silicon layer.