US4746961A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field effect transistor
Assignee: Hitachi Ltd
•
Filing: 1987-06-08
•
Granted: 1988-05-24
•
Expires: 2007-06-08
Abstract
Abstract This invention relates to the structure of a field effect transistor, which is suitable for liquid crystal display of an active matrix scheme and there is disclosed a new structure for the field effect transistor, in which at least one of the source region and the drain region is of multi-layered structure, in which high impurity concentration portions and low impurity concentration portions are alternately superposed on each other.
Inventors
- 👤 Nobutake Konishi
- 👤 Kenji Miyata
- 👤 Yoshikazu Hosokawa
- 👤 Takaya Suzuki
- 👤 Akio Mimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:35
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6721
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
113 words
A field effect transistor comprising: a source region and a drain region formed in a semiconductor layer; a channel region disposed between said source region and said drain region in said semiconductor layer; and a gate electrode disposed opposite to said channel region through an insulating film; whereby at least one of said source region and said drain region is of multi-layered structure, in which high impurity concentration portions and low impurity concentration portions are alternately superposed on each other so that a high impurity concentration portion is in contact with said channel region and that another high impurity concentration portion is in contact with a source electrode and a drain electrode, respectively.
Claim 2
Dependent Claim
113 words
A field effect transistor comprising: a source region and a drain region formed in a semiconductor layer; a channel region disposed between said source region and said drain region in said semiconductor layer; and a gate electrode disposed opposite to said channel region through an insulating film; whereby at least one of said source region and said drain region is of multi-layered structure, in which high impurity concentration portions and low impurity concentration portions are alternately superposed on each other so that a high impurity concentration portion is in contact with said channel region and that another high impurity concentration portion is in contact with a source electrode and a drain electrode, respectively.
Claim 3
Dependent Claim
34 words
A field effect transistor according to claim 1, in which the interfaces forming junctions between said high impurity concentration portions and said low impurity concentration portions terminate at the surface of said semiconductor layer.
Claim 4
Dependent Claim
35 words
A field effect transistor according to claim 1, in which all of said source region, said drain region and said channel region are of either one of the p conductivity type and n conductivity type.
Claim 5
Dependent Claim
47 words
A field effect transistor according to claim 1, in which said high impurity concentration portions and said low impurity concentration portions of said source region and said drain region and the channel region are made of either one of amorphous and polycrystalline semiconductors alone or combinations thereof.
Claim 6
Dependent Claim
20 words
A field effect transistor according to claim 1, in which said low impurity concentration portions are in the intrinsic state.
Claim 7
Dependent Claim
39 words
A field effect transistor according to claim 1, in which said source region and said drain region are of first conductivity type and the channel region is of second conductivity type, which is opposite to said first conductivity type.
Claim 8
Dependent Claim
28 words
A field effect transistor according to claim 1, in which the number of said high impurity concentration portions constituting said alternately superposed multilayered structure is at least three.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-24 | 1991-11-23 | 1992-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-24 | 1995-11-23 | 1996-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-24 | 1999-11-23 | 2000-05-24 | $7700.00 | Window Closed / Lapsed |