Abstract A phase locked loop circuit for producing a control signal with a predetermined phase relationship to an input signal includes a first counter which counts a reference clock signal and is supplied from a control circuit with first and second signals. The first counter operates in a normal mode in which a count value is changed one by one when both, the first and second signals are not supplied, in a skip mode in which a first predetermined count value is skipped when the first signal is supplied, and in a repeat mode in which a second predetermined count value is repeated when the second signal is supplied. A second counter is provided, which perform a count operation in synchronism with the reference clock signal under the control of an output of the first counter to produce the control signal. The loop circuit further includes a phase comparator which produces phase difference data representative of a phase difference between the input signal and the control signal. The control circuit supplies the first and second signals to the first counter in response to the phase difference data to command the first counter so as to operate in one of the normal, skip and repeat modes a plurality of times during one cycle period of the control signal.
A phase locked loop circuit for producing a control signal with a predetermined phase relationship to an input signal, comprising a first counter counting a reference clock signal and operating in a normal mode wherein a count value thereof is changed one by one when both of first and second signals are not supplied thereto, in a skip mode wherein a first predetermined count value is skipped when said first signal is supplied thereto and in a repeat mode wherein a second predetermined count value is repeated when said second signal is supplied thereto, a second counter performing a count operation in synchronism with said reference clock signal under control of an output of said first counter to produce said control signal, a phase comparator producing phase difference data representative of a phase difference between said control signal and said input signal, and control means responsive to said phase difference data for operatively producing said first and second signals to command said first counter to operate in at least one mode of said normal, skip and repeat modes a plurality of times during one cycle period of said control signal.
Claim 2
Dependent Claim
190 words
A phase locked loop circuit for producing a control signal with a predetermined phase relationship to an input signal, comprising a first counter counting a reference clock signal and operating in a normal mode wherein a count value thereof is changed one by one when both of first and second signals are not supplied thereto, in a skip mode wherein a first predetermined count value is skipped when said first signal is supplied thereto and in a repeat mode wherein a second predetermined count value is repeated when said second signal is supplied thereto, a second counter performing a count operation in synchronism with said reference clock signal under control of an output of said first counter to produce said control signal, a phase comparator producing phase difference data representative of a phase difference between said control signal and said input signal, and control means responsive to said phase difference data for operatively producing said first and second signals to command said first counter to operate in at least one mode of said normal, skip and repeat modes a plurality of times during one cycle period of said control signal.
Claim 3
Dependent Claim
21 words
The circuit as claimed in claim 1, wherein said first and second predetermined count values are the same as each other.
Claim 4
Dependent Claim
45 words
The circuit as claimed in claim 1, further comprising means responsive to an output of said second counter for producing a plurality of state signals during one cycle of said control signal, said control means controls said first counter in accordance with said state signals.