US4780895A
Expired / Lapsed
US
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Circuit for stabilizing the rate at which pulses appear
Assignee: Alcatel CIT SA
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Filing: 1987-06-19
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Granted: 1988-10-25
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Expires: 2007-06-19
Abstract
Abstract The circuit comprises two counters, one of which (A) operates at the irregular rate of asynchronous pulses applied to its count input (2), the other of which (B) operates at a regular rate which is not less than the average admissible rate for the asynchronous pulses, being clocked by an oscillator (5) providing pulses at a stable rate, a comparator (6) inhibiting the oscillator (5) each time the counter (B) catches up the counter (A) and a catch-up preventing control logic circuit (9) inhibiting the counter (A) whenever it tends to catch up the counter (B).
Inventors
- 👤 Philippe Paul
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:59
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0992
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
182 words
A circuit for stabilizing the rate at which asynchronous pulses appear, the circuit comprising: a first pulse counter of the asynchronous type provided with a count input receiving the asynchronous pulses, an inhibit input, and parallel outputs, and having initial stages with an operating speed compatible with the maximum frequency at which the asynchronous pulses succeed one another; an oscillator having an inhibit input and delivering output pulses at a stable rate; a second pulse counter provided with parallel outputs and with a count input receiving pulses from the oscillator; a comparator having comparison inputs connected to outputs of equal significance from the two counters and having an equality detection output connected to the inhibit input of the oscillator, said comparator inhibiting the oscillator in the event of the counts in the two counters being equal; and a catch-up preventing control logic circuit controlled by the outputs from the two counters and acting on the inhibit input of the first counter in such a manner as to inhibit said first counter when it is in danger of catching up the second counter.
Claim 2
Dependent Claim
182 words
A circuit for stabilizing the rate at which asynchronous pulses appear, the circuit comprising: a first pulse counter of the asynchronous type provided with a count input receiving the asynchronous pulses, an inhibit input, and parallel outputs, and having initial stages with an operating speed compatible with the maximum frequency at which the asynchronous pulses succeed one another; an oscillator having an inhibit input and delivering output pulses at a stable rate; a second pulse counter provided with parallel outputs and with a count input receiving pulses from the oscillator; a comparator having comparison inputs connected to outputs of equal significance from the two counters and having an equality detection output connected to the inhibit input of the oscillator, said comparator inhibiting the oscillator in the event of the counts in the two counters being equal; and a catch-up preventing control logic circuit controlled by the outputs from the two counters and acting on the inhibit input of the first counter in such a manner as to inhibit said first counter when it is in danger of catching up the second counter.
Claim 3
Dependent Claim
153 words
A circuit according to claim 1 having two counters of capacity not less than 2 N -1, where N is an integer greater than 1, wherein said catch-up preventing control logic circuit comprises first means for generating an inhibit instruction for the first counter when the first counter reaches 0 modulo 2 N while the second counter is in a count state lying in the range 0 to 2 N-1 -1 modulo 2 N , and to remove this instruction only when the second counter reaches 2 N-1 modulo 2 N , and second means for generating an inhibit instruction for the first counter when the first counter reaches 2 N-1 modulo 2 N while the second counter is in a count state lying in the range 2 N-1 and 2 N -1 modulo 2 N , and for removing this instruction only when the second counter reaches 0 modulo 2 N .
Claim 4
Dependent Claim
112 words
A circuit according to claim 2, wherein said first means comprise a first bistable held in the rest state by a logic level 1 on the output of significance 2 N-1 of the second counter and triggered by a transition from logic level 1 to logic level 0 in the output of significance 2 N-1 of the first counter, and in that said second means comprise a second bistable held at rest by a logic level 0 on the output of significance 2 N-1 of the second counter and triggered by a transition from logic level 0 to logic level 1 in the output of significance 2 N-1 of the first counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-25 | 1992-04-25 | 1992-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-25 | 1996-04-25 | 1996-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-25 | 2000-04-25 | 2000-10-25 | $7700.00 | Window Closed / Lapsed |