Digital phase and frequency detector

Claim 2

A digital signal detector comprising: means for providing a reference signal at a frequency f 1 and phase p 1 ; means for providing an input signal representative of a signal at a frequency f 2 and phase p 2 ; means for providing clock pulses; count means responsive to said reference signals, said input signals, and said clock pulses for counting said clock pulses when p 1 differs from p 2 and when f 1 differs from f 2 , and for providing output signals indicating phase and frequency differences when clock pulse counts exceed preselected count values.

Claim 3

A digital signal detector in accordance with claim 1 wherein said count means includes: first synchronizing means coupled to receive said input signal and said clock pulses for providing said input signal at a first output terminal and a signal complementary to said input signal at a second output terminal with each received clock pulse; and first and second up-down counter means having enable terminals coupled respectively to said first and second output terminals of said first synchronizing means, and count direction control terminals coupled to receive said reference signal for counting clock pulses coupled thereto and providing output pulses at overflow terminals when said clock pulse counts exceed preselected count values.

Claim 4

A digital signal detector in accordance with claim 2 wherein said count means further includes: gate means coupled to receive said input signal and a signal representative of said reference signal for providing a signal having a predetermined logic level at an output terminal when either but not both, said input signal or said signal representative of said reference signal are at said predetermined logic level and a logic level complementary to said predetermined logic level otherwise, second synchronizing means having an input terminal coupled to said output terminal of said gate means for providing said gate means output signal at a first output terminal, and a signal complementary to said gate means output signal at a second output terminal, and third and fourth up-down counter means having enable terminals coupled respectively to said first and second output terminals of said second scynchronizing means, and count direction control terminals coupled to receive said signal representative of said reference signal for counting clock pulses coupled thereto and providing output pulses at overflow terminals when said clock pulse counts exceed preselected count values.

Claim 5

A digital signal detector in accordance with claim 3 wherein said count means includes: first overflow counter means having up-down control terminals coupled to said overflow terminals of said first and second up-down counters respectively for providing carry and borrow pulses in accordance with clock pulse counts that exceed loaded count values; second overflow counter means having up-down control terminals coupled to said overflow terminals of said third and fourth up-down counters respectively for providing carry and borrow pulses in accordance with clock pulse counts that exceed loaded count values; first and second shift register means respectively coupled to receive said carry and borrow pulses from said first and second overflow counter means for serial storage in a plurality of register stages having individual output terminals; and frequency offset register means coupled to an output terminal of a selected one of said plurality of register stages for establishing corrected frequency control signals to alter said reference signal frequency in response to signals received from said selected one stage.

Claim 6

A digital signal detector in accordance with claim 4 wherein said count means further includes up-down logic means having input terminals coupled to said overflow terminals of said first, second, third, and fourth up-down counter means and an output terminal coupled to said frequency offset register means for establishing correction directions in establishing said frequency control signals.

Claim 7

A digital signal detector in accordance with claim 5 further including multiplexing means coupled to receive signals representative of said reference signal for sequentially providing enabling signals to a multiplicity of output terminals one of which is coupled to enable terminals of said third and fourth up-down counters; and switch means coupled to receive enabling signals from said multiplexing means having an output terminal coupled to said count direction control terminals of said first and second up-down counter means, a first input terminal coupled to receive said reference signal and a second input terminal for selectively coupling said first and second input terminals to an output terminal in response to said enabling signals; and divider means coupled between said reference signal means and said second input terminal of said switch means for reducing said frequency f 1 by a predetermined factor.