Multi-layer circuit structure with thin semiconductor channels

Claim 2

A multiple-layer semiconductor device comprising a single-crystal substrate and a plurality of stacked sandwiches of material, each said sandwich comprising a lower layer of a II-VI single crystal material serving as an insulator; a layer of a III-V single crystal material, at least portions of which have a thickness between about 50 Å and 100 Å, so that said portions have a semiconductor characteristic; an outer layer of said II-VI material serving as an insulator; and regions of said III-V material at selected locations through said lower and outer II-VI layers to serve as conductors in contact with said portions of said III-V material layer.

Claim 3

The multiple-layer device of claim 1 wherein said III-V material is of a first element selected from the group consisting of Al, Ga, In, and Tl, and a second element selected from the group consisting of P, As, Sb, Bi.

Claim 4

The multiple-layer device of claim 1 wherein said II-VI material is of a first element selected from the group consisting of Zn, Cd, Hg and a second element selected from the group consisting of S, Se, Te and Po.

Claim 5

The multiple-layer semiconductor device of claim 1 wherein said II-VI and III-V layers are grown epitaxially on one another.

Claim 6

The multiple-layer semiconductor device of claim 1 further comprising additional insulating layers of said II-VI material between successive ones of said sandwiches and additional layers of said III-V material on said additional II-VI material layers serving as conductive shields.

Claim 7

A multiple-layer semiconductor device comprising a substrate, a plurality of epitaxially-grown CdTe-InSb-CdTe sandwich layers arranged one above the next on said substrate and each including a lower CdTe layer serving as an insulator, and an InSb layer sandwiched therebetween and of a finite thickness less than 100 Å to serve as a semiconductor channel; with patterned grooves formed in the CdTe layers which are filled with epitaxially grown InSb material serving as conductors to contact said InSb layer; additional CdTe insulating layers and also InSb barrier layers interleaved between successive ones of said sandwich layers; and means interconnecting the InSb conductors of said sandwich layers.

Claim 8

A multiple-layer semiconductor device comprising a substrate, a plurality of epitaxially-grown CdTe-InSb-CdTe sandwich layers arranged one above the next on said substrate and each including a lower CdTe layer serving as an insulator, and an InSb layer sandwiched therebetween and of a finite thickness less than 100 Å to serve as a semiconductor channel; with patterned grooves formed in the CdTe layers which are filled with epitaxially grown InSb material serving as conductors to contact said InSb layer; additional CdTe insulating layers and also InSb barrier layers interleaved between successive ones of said sandwich layers; and means interconnecting the InSb conductors of said sandwich layers.

Claim 9

The multiple-layer semiconductor device of claim 6 wherein said substrate is semi-insulating single crystal Si.

Claim 10

The multiple-layer semiconductor device of claim 6 wherein said substrate is semi-insulating single crystal GaAs.

Claim 11

The multiple-layer semiconductor device of claim 6 wherein there are from ten to fifty of said sandwich layers.

Claim 12

The multiple-layer semiconductor device of claim 6 wherein said CdTe layers and said InSb layers are substantially single crystalline.

Claim 13

A multiple-layer semiconductor device comprising a single-crystal substrate, and a plurality of alternate epitaxially grown layers of a III-V material and a II-VI material, said II-VI material serving as an insulator, at least certain ones of said layers of III-V material having a thickness less than about 100 Å so as to have semiconductor properties, at least certain others of said layers of said III-V material having a thickness of significantly greater than 100 Å so as to have conductor properties; and regions of said III-V material disposed through the II-VI material at selected locations to serve as conductors in contact with said III-V layers of less than 100 Å; wherein said II-VI material and said III-V material are selected so as to have a lattice mismatch of less than about 0.1 percent.

Claim 14

A multiple-layer semiconductor device comprising a single-crystal substrate, and a plurality of alternate epitaxially grown layers of a III-V material and a II-VI material, said II-VI material serving as an insulator, at least certain ones of said layers of III-V material having a thickness less than about 100 Å so as to have semiconductor properties, at least certain others of said layers of said III-V material having a thickness of significantly greater than 100 Å so as to have conductor properties; and regions of said III-V material disposed through the II-VI material at selected locations to serve as conductors in contact with said III-V layers of less than 100 Å; wherein said II-VI material and said III-V material are selected so as to have a lattice mismatch of less than about 0.1 percent.