US4972102A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single-ended sense amplifier with dual feedback and a latching disable mode that saves power
Assignee: NXP USA Inc
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Filing: 1989-05-08
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Granted: 1990-11-20
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Expires: 2009-05-08
Abstract
Abstract An integrated circuit is disclosed with a logic network having an output coupled to a sense node and having a virtual ground node, and with a sense amplifier having a sensing circuit coupled to the sense node to provide an output signal, charging and discharging feedback circuits coupled to the sense node that limit the swing of the sense amplifier, and an enable control to enable and disable the sense amplifer. In one embodiment in a CMOS integrated circuit a parallel network of n-channel transistors has an output connected to a sense node of a sense amplifier. A sensing inverter and a feedback inverter are connected to this sense node. The switchpoint of the feedback inverter is substantially higher than the switchpoint of the sensing inverter. A charging n-channel transistor is connected between the sense node and a power supply for charging the sense node, and the output of the feedback inverter is connected to the gate of the charging transistor. A discharging n-channel transistor is connected in series between the parallel network and ground. The gate of the discharging transistor is coupled to the sense node. The sense amplifier can enter a power-saving disable mode, and entry is controlled by a sense amplifier enable signal. This mode has two possible states corresponding to the state of the sense amplifier immediately preceding disablement and enables the sense amplifier to avoid output glitches when leaving the disabled mode. The sense amplifier uses two negative feedback loops, including the charging and discharging n-channel transistors, to limit the swing on the sense node, and this swing is substantially independent of the number of parallel transistors that are conductive.
Inventors
- 👤 Richard Reis
- 👤 R. A. Garibay, Jr.
- 👤 Jesse R. Wilson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 00:44
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855; H03K19/0008; H03K19/0016; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
136 words
An integrated circuit, comprising: a logic network coupled between a sense node and a virtual ground node; sensing means, coupled to said sense node, for detecting a logic state of said sense node corresponding to a voltage present on said sense node, said sensing means providing an output signal having a logic state corresponding to the logic state of said sense node; charging means, coupled between said sense node and a first power supply terminal, for providing an impedance therebetween responsive to an impedance control signal; feedback means, coupled to said sense node and said charging means, for providing said impedance control signal responsive to said sense node; and discharging means, coupled between said virtual ground node and a second power supply terminal, for providing an impedance therebetween according to the voltage on said sense node.
Claim 2
Dependent Claim
136 words
An integrated circuit, comprising: a logic network coupled between a sense node and a virtual ground node; sensing means, coupled to said sense node, for detecting a logic state of said sense node corresponding to a voltage present on said sense node, said sensing means providing an output signal having a logic state corresponding to the logic state of said sense node; charging means, coupled between said sense node and a first power supply terminal, for providing an impedance therebetween responsive to an impedance control signal; feedback means, coupled to said sense node and said charging means, for providing said impedance control signal responsive to said sense node; and discharging means, coupled between said virtual ground node and a second power supply terminal, for providing an impedance therebetween according to the voltage on said sense node.
Claim 3
Dependent Claim
23 words
The integrated circuit of claim 1 further comprising: control means, coupled to the discharging means, for disabling the operation of said logic network.
Claim 4
Dependent Claim
38 words
The integrated circuit of claim 2 further comprising: latching means, coupled to the sensing means, for coupling said output signal of said sensing means to said sense node when said logic network is disabled by said control means.
Claim 5
Dependent Claim
24 words
The integrated circuit of claim 1 wherein the sensing means, the charging means, the feedback means, and the discharging means comprise only enhancement-type transistors.
Claim 6
Dependent Claim
134 words
An integrated circuit, comprising: a logic network coupled between a sense node and a virtual ground node; sensing means, coupled to said sense node, for providing an output signal representative of a voltage present on said sense node; a first inverter having an input coupled to said sense node and an output having a voltage corresponding to the voltage of aid sense node; a first transistor having a control terminal coupled to said output of said first inverter, a first current terminal coupled to a first power supply terminal, and a second current terminal coupled to said sense node; and a second transistor having a control terminal coupled to said sense node, a first current terminal coupled to said virtual ground node, and a second current terminal coupled to a second power supply terminal.
Claim 7
Dependent Claim
134 words
An integrated circuit, comprising: a logic network coupled between a sense node and a virtual ground node; sensing means, coupled to said sense node, for providing an output signal representative of a voltage present on said sense node; a first inverter having an input coupled to said sense node and an output having a voltage corresponding to the voltage of aid sense node; a first transistor having a control terminal coupled to said output of said first inverter, a first current terminal coupled to a first power supply terminal, and a second current terminal coupled to said sense node; and a second transistor having a control terminal coupled to said sense node, a first current terminal coupled to said virtual ground node, and a second current terminal coupled to a second power supply terminal.
Claim 8
Dependent Claim
23 words
The integrated circuit of claim 5 wherein the switchpoint of said first inverter is substantially higher than the switchpoint of said sensing means.
Claim 9
Dependent Claim
165 words
The integrated circuit of claim 5 further comprising: a first transmission gate having a first input/output terminal coupled to said control terminal of said second transistor and a second input/output terminal coupled to said sense node, said first transmission gate controlled by a sense amplifier enable signal; a third transistor having a first current terminal coupled to said control terminal of said second transistor and a second current terminal coupled to the second power supply terminal, said third transistor controlled by said sense amplifier enable signal; a second transmission gate having a first input/output terminal coupled to said sense node and a second input/output terminal coupled to said output of said sensing means, said second transmission gate controlled by said sense amplifier enable signal; and a fourth transistor having a first current terminal coupled to said first power supply terminal and a second current terminal coupled to said first current terminal of said first transistor, said fourth transistor controlled by said sense amplifier enable signal.
Claim 10
Dependent Claim
28 words
The integrated circuit of claim 5 wherein said logic network comprises at least two transistors having independent control terminals, common first current terminals, and common second current terminals.
Claim 11
Dependent Claim
220 words
An integrated circuit, comprising: a logic network coupled between a sense node and a virtual ground node; sensing means, coupled to said sense node, for detecting a logic state of said sense node corresponding to a voltage present on said sense node, said sensing means providing an output signal having a logic state corresponding to the logic state of said sense node; charging means, coupled between said sense node and a first power supply terminal, for providing an impedance therebetween responsive to an impedance control signal; feedback means, coupled to said sense node and said charging means, for providing said impedance control signal responsive to said sense node; a discharging transistor having a first current terminal coupled to said virtual ground node, a second current terminal coupled to a second power supply terminal, and a control terminal coupled to said sense node, said discharging transistor providing an impedance between the virtual ground node and the second power supply terminal according to the voltage on said sense node; a first transmission gate having a first input/output terminal coupled to the control terminal of said discharging transistor and a second input/output terminal coupled to said sense node; and a second transmission gate having a first input/output terminal coupled to said output signal and a second input/output terminal coupled to said sense node.
Claim 12
Dependent Claim
220 words
An integrated circuit, comprising: a logic network coupled between a sense node and a virtual ground node; sensing means, coupled to said sense node, for detecting a logic state of said sense node corresponding to a voltage present on said sense node, said sensing means providing an output signal having a logic state corresponding to the logic state of said sense node; charging means, coupled between said sense node and a first power supply terminal, for providing an impedance therebetween responsive to an impedance control signal; feedback means, coupled to said sense node and said charging means, for providing said impedance control signal responsive to said sense node; a discharging transistor having a first current terminal coupled to said virtual ground node, a second current terminal coupled to a second power supply terminal, and a control terminal coupled to said sense node, said discharging transistor providing an impedance between the virtual ground node and the second power supply terminal according to the voltage on said sense node; a first transmission gate having a first input/output terminal coupled to the control terminal of said discharging transistor and a second input/output terminal coupled to said sense node; and a second transmission gate having a first input/output terminal coupled to said output signal and a second input/output terminal coupled to said sense node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-19 | 1994-05-21 | 1994-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-19 | 1998-05-21 | 1998-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-19 | 2002-05-21 | 2002-11-20 | $7700.00 | Window Closed / Lapsed |