Fully compensated emitter coupled logic gate

Claim 1

A circuit for minimizing voltage excursions on the emitter output terminals of an emitter-follower coupled logic gate due to temperature changes comprising: a. an emitter-follower current switch logic gate having at least one input switching transistor and a reference transistor; b. a first common node and a first current source connected thereto for providing current for either said input switching transistor or said reference transistor; c. said first common node being connected to the emitter terminals of said input switching transistor and said reference transistor; d. a second node connected to the collector terminal of said input switching transistor, and a first impedance means connected between said second node and a first supply means, e. a third node connected to the collector of said reference transistor, and a second impedance means connected between said third node and the first supply means; f. first and second emitter-follower output transistors connected at their base terminals to said second and third nodes, respectively; g. the emitter terminals of said first and second emitter-follower output transistors being responsive to logical input signals at the base terminal of said input switching transistor for generating predetermined logical output signals; h. circuit means connected to said second and third nodes for minimizing voltage excursions of the logical output signals being generated from a predetermined one of said emitter follower output transistors having its base terminal connected to the collector terminal of a nonconducting input switching transistor or a nonconducting reference transistor, and i. said circuit means comprising a second current source for continuously generating a predetermined amount of current, j. switching means connected to said second current source and to said second and third nodes for selectively applying said predetermined amount of current only to said second or said third node.