Temperature compensated current-mode logic circuit

Claim 2

A logic circuit for providing both high and low output logic levels which are substantially temperature independent, comprising: a pair of parallel-connected input transistors having coupled emitters and coupled collectors; biasing means for connecting a power supply across the collectors and emitters of said input transistors; a pair of output circuits which each receive signals from the collectors of said input transistors and derive output signals therefrom, one output signal being of one level while the other is of a different level, the difference between said levels being readily detectable; and a stabilizing circuit means coupled between said pair of output circuit mEans, said stabilizing circuit means including a resistor in series with a pair of parallel oppositely-poled PN junctions, said stabilizing circuit means maintaining the two different output levels from each of said output circuit means substantially constant over a range of changes in ambient temperature.

Claim 3

The circuit of claim 1 further characterized by a third transistor having its emitter coupled to the emitters of said pair of input transistors, the collectors of said input transistors forming a node, said third transistor and said input transistors together forming a current switch, said stabilizing circuit means being coupled between said node and the collector of the said third transistor.

Claim 4

The circuit of claim 2 further characterized by a current source series-coupling the said coupled emitters of said input transistors and one power supply terminal.

Claim 5

The circuit of claim 3 further characterized by said current source including a fourth transistor in series between said coupled emitters of said input transistors and said one power supply terminal.

Claim 6

The logic circuit of claim characterized further characterized by said biasing means adapted to divide the power supply voltage proportionally, the portion between the other power supply terminal and the base of said third transistor being approximately equal to the voltage between the base of said fourth transistor and the one power supply terminal and being approximately equal to one-half the portion between the respective bases of said third and fourth transistor.

Claim 7

The circuit of claim 5 further characterized by said voltage division being accomplished by three series-coupled resistors having two nodes therebetween coupling the said one power supply terminal in said circuit to the other power supply terminal.

Claim 8

The circuit of claim 6 further characterized by one of said resistor nodes being coupled to the base of said fourth transistor and the other of said resistor nodes being coupled to the base of said third transistor.

Claim 9

The circuit of claim 6 further characterized by the value of the center resistor being approximately equal to twice the value of the other two resistors.

Claim 10

The logic circuit of claim 4 further characterized by: a fifth transistor having its emitter-collector circuit coupled between the other power supply terminal and the base of said third transistor; a sixth transistor having its emitter-collector circuit coupled between the respective bases of said third and fourth transistors; a first resistor coupling the base of said fifth transistor to said other power supply terminal; one or more series-connected diodes coupling the respective bases of said fifth sand sixth transistors; second and third diodes and a second resistor all connected in series between said one power supply terminal and the base of said sixth transistor; and a third resistor coupling the emitter of said sixth transistor to said one power supply terminal.

Claim 11

The logic circuit of claim 9 further characterized by a fourth resistor in series with said one or more series-connected diodes coupling the bases of said fifth and sixth transistor, the number of said series-connected diodes being greater than one.

Claim 12

The logic circuit of claim 10 further characterized by the value of the sum of the resistances of said second and fourth resistors being proportional to the value of the resistance of said first resistor, the proportionality constant being (n-1), wherein n is equal to the number of said series-connected diodes.

Claim 13

The logic circuit of claim 11 further characterized by said third diode having one terminal coupled to said one power supply terminal and by said second resistor series-coupling said second and third diodes, said third resistor series-coupling the emitter of said sixth transistor to the other terminal of said third diode.

Claim 14

The logic circuit of claim 11 with ''''n'''' being equal to 2.

Claim 15

The circuIt of claim 1 further characterized by said biasing means including a resistor coupled between the collector of one of said pair of input transistors and the other terminal of said power supply.

Claim 16

The circuit of claim 14 further characterized by said resistor having substantially the same value as the resistor in series with said pair of parallel PN junctions.

Claim 17

The circuit of claim 15 further characterized by a third transistor having its emitter coupled to the emitters of said pair of input transistors, the collectors of said input transistors forming a node, said third transistor and said input transistors together forming a current switch, said stabilizing circuit means being coupled between said node and the collector of the said third transistor, and said pair of output circuit means including seventh and eighth transistors, the collectors of which are coupled to said other terminal of said power supply, the bases of which are coupled, respectively, to one or the other of the collector of said third transistor or said collector node of said input transistors, the desired output signals thereby appearing at the respective emitters of said seventh and eighth transistors.

Claim 18

In a logic circuit having: a pair of parallel-connected input transistors having coupled emitters and coupled collectors; a pair of output circuits for deriving two output signals from the collectors of said input transistors, one output signal being of one level while the other is of a different level, the difference between said levels being readily detectable, one of said pair of output circuits being connected to the coupled collectors of said pair of parallel-connected input transistors; a third transistor having its emitter coupled to the emitters of said pair of input transistors and its collector coupled to the other of said pair of output circuits, said third transistor and said input transistors together forming a current switch; and a current source series-coupling the said coupled emitters of said input transistors to one power supply terminal, said current source including a fourth transistor having its emitter-collector circuit coupled between said coupled emitters of said input transistors and said one power supply terminal; a stable reference source, comprising: a. a fifth transistor having its emitter-collector circuit coupled between the other power supply terminal and the base of said third transistor; b. a sixth transistor having its emitter-collector circuit coupled between the respective bases of said third and fourth transistors; c. a first resistor coupling the base of said fifth transistor to said other power supply terminal; d. one or more series-connected diodes coupling the respective bases of said fifth and sixth transistors; e. second and third diodes and a second resistor all connected in series between said one power supply terminal and the base of said sixth transistor; and a third resistor coupling the emitter of said sixth transistor to said one power supply terminal.

Claim 19

In a logic circuit having: a pair of parallel-connected input transistors having coupled emitters and coupled collectors; a pair of output circuits for deriving two output signals from the collectors of said input transistors, one output signal being of one level while the other is of a different level, the difference between said levels being readily detectable, one of said pair of output circuits being connected to the coupled collectors of said pair of parallel-connected input transistors; a third transistor having its emitter coupled to the emitters of said pair of input transistors and its collector coupled to the other of said pair of output circuits, said third transistor and said input transistors together forming a current switch; and a current source series-coupling the said coupled emitters of said input transistors to one power supply terminal, said current source including a fourth transistor having its emitter-collector circuit coupled between said coupled emitters of said input transistors and said one power supply terminal; a stable reference source, comprising: a. a fifth transistor having its emitter-collector circuit coupled between the other power supply terminal and the base of said third transistor; b. a sixth transistor having its emitter-collector circuit coupled between the respective bases of said third and fourth transistors; c. a first resistor coupling the base of said fifth transistor to said other power supply terminal; d. one or more series-connected diodes coupling the respective bases of said fifth and sixth transistors; e. second and third diodes and a second resistor all connected in series between said one power supply terminal and the base of said sixth transistor; and a third resistor coupling the emitter of said sixth transistor to said one power supply terminal.

Claim 20

The logic circuit of claim 17 further characterized by a fourth resistor in series with said one or more series-connected diodes coupling the bases of said fifth and sixth transistor, the number of said series-connected diodes being greater than one.

Claim 21

The logic circuit of claim 18 further characterized by the value of the sum of the resistances of said second and fourth resistors being proportional to the value of the resistance said first resistor, the proportionality constant being (n- 1), wherein n is equal to the number of said series-connected diodes.

Claim 22

The logic circuit of claim 17 further characterized by said third diode having one terminal coupled to said one power supply terminal and by said second resistor series-coupling said second and third diodes, said third resistor series-coupling the emitter of said sixth transistor to the other terminal of said third diode.