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US4969823A
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Integrated circuit with complementary junction-isolated bipolar transistors and method of making same
Assignee: Analog Devices Inc
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Filing: 1988-05-05
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Granted: 1990-11-13
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Expires: 2008-05-05
Abstract
Abstract Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and novel chip made by such process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.
Inventors
- 👤 Jerome F. Lapham
- 👤 Brad W. Scharf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:48
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/67; H10D84/673; H10D84/01; H10D84/0112; H10D84/0119; H10D84/0121; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
198 words
The method of making an integrated circuit with complementary junction-isolated bipolar transistors comprising the following steps (not necessarily in the order recited): implanting P-type material in an N-type substrate to form a sub-collector for a pnp transistor and to form a P-well for isolating the collector of an npn transistor; implanting and diffusing N-type material in said substrate to form up regions to (a) partially establish said npn collector in said P-well and (b) partially establish an isolation wall for said pnp transistor; growing a P-type epitaxial (epi) layer over said N-type substrate; implanting and diffusing N-type material into said epi layer to form down regions to (1) merge with said N-type collector up region and (2) merge with said N-type isolation up region to form said isolation wall; implanting and diffusing P-type material in said epi layer to form the base for said npn transistor; implanting and diffusing N-type material in said epi layer to form the emitter for said npn transistor; implanting and diffusing N-type material in said epi layer to form the base for said pnp transistor; and implanting and diffusing P-type material in said epi layer to form the emitter for said pnp transistor.
Claim 2
Independent Claim
198 words
The method of making an integrated circuit with complementary junction-isolated bipolar transistors comprising the following steps (not necessarily in the order recited): implanting P-type material in an N-type substrate to form a sub-collector for a pnp transistor and to form a P-well for isolating the collector of an npn transistor; implanting and diffusing N-type material in said substrate to form up regions to (a) partially establish said npn collector in said P-well and (b) partially establish an isolation wall for said pnp transistor; growing a P-type epitaxial (epi) layer over said N-type substrate; implanting and diffusing N-type material into said epi layer to form down regions to (1) merge with said N-type collector up region and (2) merge with said N-type isolation up region to form said isolation wall; implanting and diffusing P-type material in said epi layer to form the base for said npn transistor; implanting and diffusing N-type material in said epi layer to form the emitter for said npn transistor; implanting and diffusing N-type material in said epi layer to form the base for said pnp transistor; and implanting and diffusing P-type material in said epi layer to form the emitter for said pnp transistor.
Claim 3
Independent Claim
160 words
The method of making an integrated circuit with complementary junction-isolated bipolar transistors comprising the following steps (not necessarily in the order recited): growing P-type epitaxial (epi) layer over an N-type substrate; implanting and diffusing N-type material to form a collector region in said epi layer for an npn transistor; implanting and diffusing N-type material to establish in said P-type epi layer an N-type isolation wall surrounding a portion of said P-type epi layer, so that said portion can serve as a collector region of a pnp transistor; implanting and diffusing P-type material in said epi layer to form a base region for said npn transistor; implanting and diffusing N-type material in said epi layer to form an emitter region for said npn transistor; implanting and diffusing N-type material in said epi layer to form a base region for said pnp transistor; and implanting and diffusing P-type material in said epi layer to form an emitter region for said pnp transistor.
Claim 4
Independent Claim
160 words
The method of making an integrated circuit with complementary junction-isolated bipolar transistors comprising the following steps (not necessarily in the order recited): growing P-type epitaxial (epi) layer over an N-type substrate; implanting and diffusing N-type material to form a collector region in said epi layer for an npn transistor; implanting and diffusing N-type material to establish in said P-type epi layer an N-type isolation wall surrounding a portion of said P-type epi layer, so that said portion can serve as a collector region of a pnp transistor; implanting and diffusing P-type material in said epi layer to form a base region for said npn transistor; implanting and diffusing N-type material in said epi layer to form an emitter region for said npn transistor; implanting and diffusing N-type material in said epi layer to form a base region for said pnp transistor; and implanting and diffusing P-type material in said epi layer to form an emitter region for said pnp transistor.
Claim 5
Dependent Claim
29 words
The method of claim 2, including the step of implanting and diffusing P-type material to form a P-well in said substrate to isolate said npn collector in said substrate.
Claim 6
Independent Claim
152 words
The method of making an integrated circuit with complementary bipolar transistors comprising the following steps (not necessarily in the order recited): growing a P-type epitaxial (epi) layer over a substrate; implanting and diffusing N-type material in said epi layer to form a collector region for an npn transistor establishing in said P-type epi layer an isolation barrier surrounding a portion of said P-type epi layer, so that said portion can serve as a collector region of a pnp transistor; implanting and diffusing P-type material in said epi layer to form a base region for said npn transistor; implanting and diffusing N-type material in said epi layer to form an emitter region for said npn transistor; implanting and diffusing N-type material in said epi layer to form a base region for said pnp transistor; and implanting and diffusing P-type material in said epi layer to form an emitter region for said pnp transistor.
Claim 7
Independent Claim
152 words
The method of making an integrated circuit with complementary bipolar transistors comprising the following steps (not necessarily in the order recited): growing a P-type epitaxial (epi) layer over a substrate; implanting and diffusing N-type material in said epi layer to form a collector region for an npn transistor establishing in said P-type epi layer an isolation barrier surrounding a portion of said P-type epi layer, so that said portion can serve as a collector region of a pnp transistor; implanting and diffusing P-type material in said epi layer to form a base region for said npn transistor; implanting and diffusing N-type material in said epi layer to form an emitter region for said npn transistor; implanting and diffusing N-type material in said epi layer to form a base region for said pnp transistor; and implanting and diffusing P-type material in said epi layer to form an emitter region for said pnp transistor.
Claim 8
Independent Claim
190 words
The method of making an integrated circuit with complementary junction-isolated bipolar transistors comprising the following steps (not necessarily in the order recited): implanting and diffusing P-type impurity in an N-type substrate to form a sub-collector for a pnp transistor; growing a P-type epitaxial (epi) layer over said N-type substrate; implanting and diffusing N-type material in said P-type epi layer to form a collector region for an npn transistor; implanting and diffusing N-type material in said P-type epi layer to establish an N-type isolation wall surrounding a portion of said P-type epi layer which is above said P-type impurity in said substrate, said surrounded portion of said P-type epi layer serving as a lightly-doped collector region for said pnp transistor so as to provide a high Early Voltage for that transistor; implanting and diffusing at least one impurity in said epi layer to form a base region for at least one of said transistors; implanting and diffusing N-type material in said epi layer to form an emitter region for said npn transistor; and implanting and diffusing P-type material in said epi layer to form an emitter region for said pnp transistor.
Claim 9
Independent Claim
190 words
The method of making an integrated circuit with complementary junction-isolated bipolar transistors comprising the following steps (not necessarily in the order recited): implanting and diffusing P-type impurity in an N-type substrate to form a sub-collector for a pnp transistor; growing a P-type epitaxial (epi) layer over said N-type substrate; implanting and diffusing N-type material in said P-type epi layer to form a collector region for an npn transistor; implanting and diffusing N-type material in said P-type epi layer to establish an N-type isolation wall surrounding a portion of said P-type epi layer which is above said P-type impurity in said substrate, said surrounded portion of said P-type epi layer serving as a lightly-doped collector region for said pnp transistor so as to provide a high Early Voltage for that transistor; implanting and diffusing at least one impurity in said epi layer to form a base region for at least one of said transistors; implanting and diffusing N-type material in said epi layer to form an emitter region for said npn transistor; and implanting and diffusing P-type material in said epi layer to form an emitter region for said pnp transistor.
Claim 10
Dependent Claim
26 words
The method of claim 5, including the steps of implanting and diffusing P-type and N-type impurities to form the bases for both of said transistors respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-12 | 1994-05-14 | 1994-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-12 | 1998-05-14 | 1998-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-12 | 2002-05-14 | 2002-11-13 | $7700.00 | Window Closed / Lapsed |