Process for fabricating a monolithic circuit with high q capacitor

Abstract

Abstract A PROCESS FOR FABRICATING A MONOLITHIC CIRCULT HAVING BOTH MATCHED COMPLEMENTARY PNP AND NPN TRANSISTORS AND DOUBLE JUNCTION CAPACITORS HAVING A HIGH Q VALUE. INSOLATED N-TYPE REGIONS FOR EACH TRANSISTOR AND THE CAPACITOR ARE FORMED BY DIFFUSING P-TYPE ISOLATION RINGS THROUGH AN N-TYPE EPITAXIAL LAYER INTO A P-TYPE SUBSTRATE. SEPARATE DIFFUSIONS ARE THEN MADE FOR THE COLLECTOR, BASE AND EMITTER OF THE PNP TRANSISTOR AND FOR THE BASE AND EMITTER OF THE NPN TRANSISTOR. THE CAPICITOR IS FORMED BY THE SAME DIFFUSIONS THAT FORM THE COLLECTOR REGION OF THE PNP TRANSISTOR AND THE DIFFUSION THAT FORMS THE EMITTER OF THE NPN TRANSISTOR. THE COLLECTOR DIFFUSION FOR THE PNP TRANSISTOR IS RELATIVELY DEEP AND THE EMITTER DIFFUSION FOR THE NPN SISTIVITY CHARGING PATH THROUGH THE P-TYPE REGION TO THE OPPOSED JUNCTIONS FORMING THE CAPACITOR.

Inventors

• 👤 Robert A Stehlin

Bibliographic Details