Non-volatile semiconductor memory with SCRAM hold cycle prior to SCRAM-to-E2 PROM backup transfer

Claim 3

The method of claim 1 including charging the backup capacitor by means of a voltage up converter to increase the amount of backup energy storage, and discharging current from the backup capacitor by means of a voltage down converter circuit to supply the internal supply voltage.

Claim 4

The method of claim 1 including removing power from the E 2 PROM during the read and/or write memory accesses by the host computer and maintaining the data maintenance voltage at a reduced level substantially less than a normal operating voltage of the SRAM while accessing of the SRAM is halted.

Claim 5

The method of claim 2 wherein the selected level of the backup capacitor voltage is approximately 100 volts and the first threshold is approximately 85 volts.

Claim 6

The method of claim 1 wherein the preselected time is at least approximately one minute.

Claim 7

The method of claim 1 including uploading data from the E 2 PROM to the SRAM if the external power supply voltage rises above the first threshold and the backup capacitor voltage rises above the second threshold.

Claim 8

The method of claim 6 including accumulating row parity information and column parity information and comparing it with previously stored row parity information and column parity information in the E 2 PROM and using results of the comparing to correct the data and storing the corrected data in the SRAM during the uploading.

Claim 9

The method of claim 7 wherein the SRAM includes a plurality of integrated circuit SRAMs and a plurality of integrated circuit E 2 PROMs, the method including subdividing each integrated circuit SRAM into a plurality of subsections and subdividing the integrated circuit E 2 PROMs into corresponding subsections, the downloading including (i) reading data in words in a first subsection of a first integrated circuit SRAM and transferring the read data into a corresponding subsection of a first integrated circuit E 2 PROM and also transferring the read data into corresponding word locations of a row parity accumulator and also into a column parity accumulator; (ii) reading data in words in a first subsection of a second integrated circuit SRAM and exclusive ORing each bit of that first subsection with a corresponding bit of the row parity accumulator and storing the result into a corresponding bit location of the row parity accumulator and exclusive ORing each bit of that first subsection with a corresponding bit of the column parity accumulator and storing the result in that corresponding bit location of the column parity accumulator; (iii) repeating step (ii) for the first subsection of each remaining integrated circuit SRAM; (iv) transferring the contents of the row parity accumulator and the column parity accumulator into the E 2 PROM.

Claim 10

The method of claim 8 wherein the uploading includes: (1) reading data in words in a first subsection of the first integrated circuit E 2 PROM and transferring that read data into the first subsection of the SRAM and also transferring that read data into corresponding word locations of the row parity accumulator and into the column parity accumulator; (2) reading data in words in a first subsection of a second integrated circuit E 2 PROM and exclusive ORing each bit with a corresponding bit of the row parity accumulator and storing the result into a corresponding bit location of the row parity accumulator, and also exclusively ORing that bit with a corresponding bit of the column parity accumulator and storing the result into a corresponding bit location of the column parity accumulator; (3) repeating step (2) for the first subsection of each remaining integrated circuit E 2 PROM; (4) comparing the row parity data in the row parity accumulator with corresponding row parity data previously stored in the E 2 PROM and comparing column parity data in the column parity accumulator with column parity data previously stored in the E 2 PROM if a mismatch occurs, and exclusively ORing an error pattern produced from the row parity data and column parity data with corresponding data transferred from the E.sup. PROM to the SRAM to produce corrected data and writing the corrected data into the SRAM.

Claim 11

The method of claim 9 including repeating steps (i) through (iv) and steps (1) through (4) for each subsection of the integrated circuit SRAMs and each subsection of the integrated circuit E 2 PROMs.

Claim 12

A non-volatile memory system including means for preventing excessive downloading of data from a volatile SRAM into an E 2 PROM in response to short duration power interruptions, the non-volatile memory system comprising in combination: (a) means for writing data into and reading data from the SRAM in response to a host computer; (b) means for enabling the host computer to continue to perform read and/or write memory accesses to the SRAM while an external power supply voltage is applied to the non-volatile memory system; (c) a backup capacitor (d) means for charging a voltage of the backup capacitor to a selected level and maintaining the selected level while the external power supply voltage is applied to the non-volatile memory system; (e) means for halting accessing of the SRAM by the host computer if the external power supply voltage falls below a first threshold; (f) means for discharging the backup capacitor to supply energy to maintain a data maintenance voltage on the SRAM if the external power supply voltage falls below the first threshold; (g) means for resuming accessing of the SRAM by the host computer if the external power supply voltage rises above the first threshold before the backup capacitor voltage falls below a second threshold; (h) means for downloading all of the data in the SRAM to the E 2 PROM while discharging the backup capacitor to supply energy to maintain an internal power supply voltage needed for the downloading if the backup capacitor voltage falls below the second threshold, the backup capacitor storing enough energy when the backup capacitor voltage is at the selected level to both effectuate the downloading and allow the halted condition to continue for at least a preselected time.

Claim 13

A non-volatile memory system including means for preventing excessive downloading of data from a volatile SRAM into an E 2 PROM in response to short duration power interruptions, the non-volatile memory system comprising in combination: (a) means for writing data into and reading data from the SRAM in response to a host computer; (b) means for enabling the host computer to continue to perform read and/or write memory accesses to the SRAM while an external power supply voltage is applied to the non-volatile memory system; (c) a backup capacitor (d) means for charging a voltage of the backup capacitor to a selected level and maintaining the selected level while the external power supply voltage is applied to the non-volatile memory system; (e) means for halting accessing of the SRAM by the host computer if the external power supply voltage falls below a first threshold; (f) means for discharging the backup capacitor to supply energy to maintain a data maintenance voltage on the SRAM if the external power supply voltage falls below the first threshold; (g) means for resuming accessing of the SRAM by the host computer if the external power supply voltage rises above the first threshold before the backup capacitor voltage falls below a second threshold; (h) means for downloading all of the data in the SRAM to the E 2 PROM while discharging the backup capacitor to supply energy to maintain an internal power supply voltage needed for the downloading if the backup capacitor voltage falls below the second threshold, the backup capacitor storing enough energy when the backup capacitor voltage is at the selected level to both effectuate the downloading and allow the halted condition to continue for at least a preselected time.

Claim 14

The non-volatile memory system of claim 11 wherein the backup capacitor charging means includes a voltage up converter to increase the amount of backup energy storage, and the backup capacitor discharging means including a voltage down converter circuit discharging current from the backup capacitor to supply the internal power supply voltage.

Claim 15

The non-volatile memory system of claim 11 including means for removing power from the E 2 PROM during the read and/or write memory accesses by the host computer, and including means for maintaining the data maintenance voltage at a reduced level substantially less than a normal operating voltage of the SRAM.

Claim 16

The non-volatile memory system of claim 12 wherein the selected level of the backup capacitor voltage is approximately 100 volts and the first threshold is approximately 85 volts.

Claim 17

The non-volatile memory system of claim 11 wherein the preselected time is at least approximately one minute.

Claim 18

The non-volatile memory system of claim 11 including means for uploading data from the E 2 PROM to the SRAM if the external power supply voltage rises above the first threshold and the backup capacitor voltage rises above the second threshold.

Claim 19

The non-volatile memory system of claim 16 including means for accumulating row parity information and column parity information and means for comparing the accumulated row parity information and the column parity information with previously stored row parity information and column parity information, respectively, in the E 2 PROM, and means for correcting the data in response to the comparing, and means for storing the corrected data in the SRAM during the uploading.

Claim 22

The method of claim 18 including uploading data from the E 2 PROM to the SRAM if the external power supply voltage rises above the first threshold and the backup capacitor voltage rises above the second threshold, and accumulating row parity information and column parity information and comparing it with previously stored row parity information and column parity information in the non-volatile backup memory and using results of the comparing to correct the data and storing the corrected data in the RAM during the uploading.

Claim 23

The method of claim 19 including storing a key word into a non-volatile, eraseable key register, encrypting data being downloaded from the RAM into the non-volatile memory using the stored key word, and decrypting data being uploaded from the non-volatile memory to the RAM using the key word, and erasing the key word from the key register to allow the data downloaded to be declassified.

Claim 24

A non-volatile memory system including means for preventing excessive downloading of data from a volatile RAM into a non-volatile backup memory, in response to short duration power interruptions, the non-volatile memory system comprising in combination: (a) means for writing data into and reading data from the RAM in response to a host computer; (b) means for enabling the host computer to continue to perform read and/or write memory accesses to the RAM while an external power supply voltage is applied to the non-volatile memory system; (c) a backup voltage source supplying a backup voltage; (d) means for halting accessing of the RAM by the host computer if the external power supply voltage falls below a first threshold; (e) means for discharging the backup voltage source to supply energy to maintain a data maintenance voltage on the RAM if the external power supply voltage falls below the first threshold; (f) means for resuming accessing of the RAM by the host computer if the external power supply voltage rises above the first threshold before the backup voltage falls below a second threshold; (g) means for downloading all of the data in the RAM to the non-volatile backup memory while discharging the backup voltage source to supply energy to maintain an internal power supply voltage needed for the downloading if the backup voltage falls below the second threshold, the backup voltage source storing enough energy to both effectuate the downloading and allow the halted condition to continue for at least a preselected time.

Claim 25

A non-volatile memory system including means for preventing excessive downloading of data from a volatile RAM into a non-volatile backup memory, in response to short duration power interruptions, the non-volatile memory system comprising in combination: (a) means for writing data into and reading data from the RAM in response to a host computer; (b) means for enabling the host computer to continue to perform read and/or write memory accesses to the RAM while an external power supply voltage is applied to the non-volatile memory system; (c) a backup voltage source supplying a backup voltage; (d) means for halting accessing of the RAM by the host computer if the external power supply voltage falls below a first threshold; (e) means for discharging the backup voltage source to supply energy to maintain a data maintenance voltage on the RAM if the external power supply voltage falls below the first threshold; (f) means for resuming accessing of the RAM by the host computer if the external power supply voltage rises above the first threshold before the backup voltage falls below a second threshold; (g) means for downloading all of the data in the RAM to the non-volatile backup memory while discharging the backup voltage source to supply energy to maintain an internal power supply voltage needed for the downloading if the backup voltage falls below the second threshold, the backup voltage source storing enough energy to both effectuate the downloading and allow the halted condition to continue for at least a preselected time.

Claim 26

The non-volatile memory system of claim 21 including means for uploading data from the non-volatile backup memory to the RAM if the external power supply voltage rises above the first threshold and the backup voltage rises above the second threshold.

Claim 27

The non-volatile memory system of claim 22 including an eraseable register storing a key word, and encryption/decryption means coupled to the eraseable register for encrypting data being downloaded from the RAM into the non-volatile memory using the key word and decrypting data being uploaded from the non-volatile memory into the RAM using the key word, and means coupled to the eraseable register for rapidly erasing the key word from the eraseable register in response to a user command.

Claim 28

The non-volatile memory system of claim 23 wherein the eraseable register is a 56-bit ferrite core register.