US4638465A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated structure microcomputer provided with non-volatile RAM memory
Assignee: STMicroelectronics SRL
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Filing: 1984-01-31
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Granted: 1987-01-20
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Expires: 2004-01-31
Abstract
Abstract An integrated structure composed of a processing unit (CPU), ROM memory, RAM memory and other optional functions, such as input/output etc., is arranged as a microcomputer, in which all or part of the RAM is a non-volatile memory which carries out during normal operation all the functions of a RAM while also being able, through suitable circuit structures, to store in a permanent (non-volatile) way the data contained therein, retaining the data when the power feed to the circuit is cut off, and recalling the same data at power turn-on. The structure provides for the handling of the non-volatile memory in its different functions, and its arrangement and compatibility with the processing unit, through suitable circuitry and control signals.
Inventors
- 👤 Paolo Rosini
- 👤 Roberto Finaurini
- 👤 Maurizio Gaibotti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:05
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
217 words
An integrated structure microcomputer, comprising: a non-volatile RAM memory; and voltage control circuitry joined to said memory, said circuitry being responsive to voltage changes on a supply line associated with said circuitry to alter a supply voltage applied by the circuitry to said memory, the memory including a matrix of non-volatile RAM cells responsive to changes in voltage supplied by the circuitry whereby data is stored in the cells, each of said cells comprising a bistable circuit with two interconnected branches, alternatively conducting and non-conducting, one of which includes a non-volatile memory element which can be electrically programmed in one or the other of two electric states as a function of the state in which said bistable circuit is at the moment of turn-off of power on said supply line and which also is able to cause the restoration of said state of the bistable circuit at the moment of power turn-on, each branch of said bistable circuit also including a control switch element controlled by the level of said power and by the state of the other branch of the bistable circuit whereby power turn-off allows the non-conducting branch of the bistable circuit to cause interdiction of the conducting branch of the same bistable circuit for consequent programming of said non-volatile memory element without current absorption.
Claim 2
Dependent Claim
217 words
An integrated structure microcomputer, comprising: a non-volatile RAM memory; and voltage control circuitry joined to said memory, said circuitry being responsive to voltage changes on a supply line associated with said circuitry to alter a supply voltage applied by the circuitry to said memory, the memory including a matrix of non-volatile RAM cells responsive to changes in voltage supplied by the circuitry whereby data is stored in the cells, each of said cells comprising a bistable circuit with two interconnected branches, alternatively conducting and non-conducting, one of which includes a non-volatile memory element which can be electrically programmed in one or the other of two electric states as a function of the state in which said bistable circuit is at the moment of turn-off of power on said supply line and which also is able to cause the restoration of said state of the bistable circuit at the moment of power turn-on, each branch of said bistable circuit also including a control switch element controlled by the level of said power and by the state of the other branch of the bistable circuit whereby power turn-off allows the non-conducting branch of the bistable circuit to cause interdiction of the conducting branch of the same bistable circuit for consequent programming of said non-volatile memory element without current absorption.
Claim 3
Dependent Claim
78 words
A microcomputer according to claim 1, wherein said control switch element comprises a transistor inserted between a respective branch of said bistable circuit and a low-voltage line provisionally switchable to a higher voltage in response to a gate connected to a further line at higher voltage switchable to ground at the moment of power turn-off, said connection including a state sensing transistor having a gate voltage dependent on the state of said other branch of the bistable circuit.
Claim 4
Dependent Claim
57 words
A microcomputer according to claim 2, wherein said non-volatile memory is of the kind having a floating gate interposed between a programming gate connected to a circuit node situated in series with a branch of the bistable circuit and two drain and source electrodes of a short-circuitable transistor inserted in the other branch of the bistable circuit.
Claim 5
Dependent Claim
25 words
A microcomputer according to claim 2, said voltage control circuitry includes respective switches controlled by a reset logic circuit responsive to a power turn-off condition.
Claim 6
Dependent Claim
38 words
A microcomputer according to claim 4, wherein each of said switches has associated therewith a voltage amplifier provided with a voltage regulator for the generation of the highest one of the voltages applied to each of said lines.
Claim 7
Dependent Claim
36 words
A microcomputer according to claim 5, wherein the voltage regulator has associated therewith a voltage increase limiter for adjusting an increase in time from said low voltage to said highest voltage in response to power turn-off.
Claim 8
Dependent Claim
32 words
A microcomputer according to claim 1 wherein said voltage control circuitry produces a high-voltage signal for charging a capacitive element to maintain power voltage level for a predetermined time after power turn-off.
References Cited (Backward Citations)
US3980935A
Cited
US4399524A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-19 | 1990-07-21 | 1991-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-19 | 1994-07-21 | 1995-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-19 | 1998-07-21 | 1999-01-20 | $7700.00 | Window Closed / Lapsed |