US4399524A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory protection system
Assignee: Sharp Corp
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Filing: 1981-02-18
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Granted: 1983-08-16
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Expires: 2001-02-18
Abstract
Abstract A memory protection system includes an auxiliary power supply source for maintaining information stored in a random access memory when the main power supply is terminated. When the main power supply voltage level becomes lower than a preselected level, a detection unit develops a control signal for applying a disabling signal to a chip selection terminal included in the random access memory, whereby a load such as a central processor unit connected to the random access memory is electrically disconnected from the random access memory to minimize the power dissipation.
Inventors
- 👤 Norio Muguruma
- 👤 Mitsuo Morihisa
- 👤 Hideyuki Akao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:21
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/141; H; H03; H03K; H03K17/00; H03K17/22; H03K17/24; H03K2217/00; H03K2217/0036
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
228 words
A memory protection system comprising: a volatile memory including a chip selection terminal and an output terminal; load means connected to said output terminal of said volatile memory; a main power supply terminal for supplying power to said volatile memory and said load means; an auxiliary power source for supplying power to said volatile memory when a voltage level derived from said main power supply terminal is lower than a preselected level; and voltage level detection means for developing a disabling signal to said chip selection terminal of said volatile memory when the voltage level derived from said main power supply terminal becomes lower than said preselected level, thereby electrically disconnecting said load means from said volatile memory when said volatile memory is supplied with power from said auxiliary power source, said voltage level detection means including, a Zener diode connected to said power supply terminal, said Zener diode being placed in a nonconductive condition when the voltage level derived from said main power supply terminal becomes lower than said preselected level; a transistor connected to said chip selection terminal of said volatile memory for applying an enabling signal in a normal operation mode; and means for placing said transistor in the nonconductive condition when said Zener diode is placed in said nonconductive condition, thereby applying said disabling signal to said chip selection terminal of said volatile memory.
Claim 2
Dependent Claim
228 words
A memory protection system comprising: a volatile memory including a chip selection terminal and an output terminal; load means connected to said output terminal of said volatile memory; a main power supply terminal for supplying power to said volatile memory and said load means; an auxiliary power source for supplying power to said volatile memory when a voltage level derived from said main power supply terminal is lower than a preselected level; and voltage level detection means for developing a disabling signal to said chip selection terminal of said volatile memory when the voltage level derived from said main power supply terminal becomes lower than said preselected level, thereby electrically disconnecting said load means from said volatile memory when said volatile memory is supplied with power from said auxiliary power source, said voltage level detection means including, a Zener diode connected to said power supply terminal, said Zener diode being placed in a nonconductive condition when the voltage level derived from said main power supply terminal becomes lower than said preselected level; a transistor connected to said chip selection terminal of said volatile memory for applying an enabling signal in a normal operation mode; and means for placing said transistor in the nonconductive condition when said Zener diode is placed in said nonconductive condition, thereby applying said disabling signal to said chip selection terminal of said volatile memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-15 | 1987-02-14 | 1987-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-15 | 1991-02-14 | 1991-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-15 | 1995-02-14 | 1995-08-16 | $7700.00 | Window Closed / Lapsed |