Data processing system incorporating a memory resident directive for synchronizing multiple tasks among plurality of processing elements by monitoring alternation of semaphore data

Claim 2

In a data processing system including a plurality of processing elements interconnected with each other and with at least one memory element by an interconnection means, each of said processing elements selectively executing program tasks, said at least one memory element including multiple memory locations identifiable by corresponding memory addresses for storing data, a method for synchronizing operation of said plurality of processing elements, said method comprising the steps of: designating a selected memory location of a selected memory element to contain semaphore data; altering, by selected ones of said plurality of processing elements, said semaphore data whereby to indicate a status of selected tasks; sending, from at least one requesting processing element to said selected memory element via said interconnecting means, a directive including (1) the address of said selected memory location, and (2) an identification of the requesting processing element sending said directive; reading in said selected memory element said semaphore data; sending said semaphore data to said requesting processing element via said interconnection means; storing said directive in said memory element; monitoring in said memory element the alteration of said semaphore data; and repeating said reading and sending steps when said semaphore data is altered.

Claim 3

A method in accordance with claim 1 wherein said step of sending said directive further includes sending a timeout value; and terminating said repeating step when said timeout value is exceeded.

Claim 4

A method in accordance with claim 1 wherein said sending step includes the step of assembling said directive in said requesting processing element.

Claim 5

A method in accordance with claim 1 wherein said storing step includes storing said directive associatively with the address of said selected memory location.

Claim 6

A method in accordance with claim 1 wherein said sending step includes sending a task identification of a requesting task performed by said requesting processing element.

Claim 7

In a data processing system including a plurality of processing elements interconnected with each other and with at least one memory element by an interconnection means, each of said processing elements selectively executing program tasks, said at least one memory element including multiple memory locations identifiable by corresponding memory addresses for storing data, a method for synchronizing operation of said plurality of processing elements, said method comprising the steps of: designating a selected memory location of a selected memory element to contain semaphore data; altering, by selected ones of said plurality of processing elements, said semaphore data whereby to indicate a status of selected tasks; sending, from at least one requesting processing element to said selected memory element via said interconnecting means, a directive including (1) the address of said selected memory location, (2) a comparison value, and (3) an identification of the requesting processing element sending said directive; reading in said selected memory element said semaphore data; comparing in said memory element said semaphore data with said comparison value; notifying said requesting processing element via said interconnection means if said semaphore data matches said comparison value; storing said directive in said selected memory element if said semaphore data does not match said comparison value; monitoring in said selected memory element the altering of said semaphore data; and repeating said reading, comparing, and notifying steps when said semaphore data is altered.

Claim 8

In a data processing system including a plurality of processing elements interconnected with each other and with at least one memory element by an interconnection means, each of said processing elements selectively executing program tasks, said at least one memory element including multiple memory locations identifiable by corresponding memory addresses for storing data, a method for synchronizing operation of said plurality of processing elements, said method comprising the steps of: designating a selected memory location of a selected memory element to contain semaphore data; altering, by selected ones of said plurality of processing elements, said semaphore data whereby to indicate a status of selected tasks; sending, from at least one requesting processing element to said selected memory element via said interconnecting means, a directive including (1) the address of said selected memory location, (2) a comparison value, and (3) an identification of the requesting processing element sending said directive; reading in said selected memory element said semaphore data; comparing in said memory element said semaphore data with said comparison value; notifying said requesting processing element via said interconnection means if said semaphore data matches said comparison value; storing said directive in said selected memory element if said semaphore data does not match said comparison value; monitoring in said selected memory element the altering of said semaphore data; and repeating said reading, comparing, and notifying steps when said semaphore data is altered.

Claim 9

A method in accordance with claim 6 and further including the step of returning said semaphore data obtained by the first one of said reading steps to said requesting processing element regardless of whether said semaphore data matches said comparison value.

Claim 10

A method in accordance with claim 7 wherein said step of sending a directive to said selected memory element further includes the step of sending a timeout value to said memory element; and terminating said repeating step when said timeout value is exceeded.

Claim 11

A method in accordance with claim 7 wherein said step of notifying said requesting processing element includes sending said semaphore data read in said reading step to said requesting processing element.

Claim 12

A method in accordance with claim 7 and further including the step of assembling said directive in said requesting processing element.

Claim 13

A method in accordance with claim 7 wherein said storing step includes the step of storing said directive associatively with the address of said selected memory location.

Claim 14

A method in accordance with claim 7 wherein said step of sending said directive includes sending an identification of a requesting task performed by said requesting processing element.

Claim 15

In a data processing system including a plurality of processing elements interconnected with each other and with at least one memory element by an interconnection means, each of said processing elements selectively executing program tasks, said at least one memory element including multiple memory locations identifiable by corresponding memory addresses for storing data, apparatus for synchronizing operation of said plurality of processing elements, comprising; means for designating a selected memory location of a selected memory element to contain semaphore data; means for altering, by selected ones of said plurality of processing elements, said semaphore data whereby to indicate a status of selected tasks; means for sending, from at least one requesting processing element to said selected memory element via said interconnecting means, a directive including (1) the address of said selected memory location, and (2) an identification of the requesting processing element sending said directive; means for reading in said selected memory element said semaphore data; means for ending said semaphore data to said requesting processing element via said interconnection means; means for storing said directive in said memory element; means for monitoring in said memory element the altering of said semaphore data; and means for activating said reading and sending means when said semaphore data is altered.

Claim 16

In a data processing system including a plurality of processing elements interconnected with each other and with at least one memory element by an interconnection means, each of said processing elements selectively executing program tasks, said at least one memory element including multiple memory locations identifiable by corresponding memory addresses for storing data, apparatus for synchronizing operation of said plurality of processing elements, comprising; means for designating a selected memory location of a selected memory element to contain semaphore data; means for altering, by selected ones of said plurality of processing elements, said semaphore data whereby to indicate a status of selected tasks; means for sending, from at least one requesting processing element to said selected memory element via said interconnecting means, a directive including (1) the address of said selected memory location, and (2) an identification of the requesting processing element sending said directive; means for reading in said selected memory element said semaphore data; means for ending said semaphore data to said requesting processing element via said interconnection means; means for storing said directive in said memory element; means for monitoring in said memory element the altering of said semaphore data; and means for activating said reading and sending means when said semaphore data is altered.

Claim 17

Apparatus in accordance with claim 41 wherein said directive further includes a timeout value; and means for terminating said activating means when said timeout value is exceeded.

Claim 18

Apparatus in accordance with claim 41 wherein said means for sending said directive includes means for assembling said directive in said requesting processing element.

Claim 19

Apparatus in accordance with claim 13 wherein said storing means includes means for storing said directive associatively with the address of said selected memory location.

Claim 20

Apparatus in accordance with claim 13 wherein said sending means includes means for sending a task identification of a requesting task performed by said requesting processing element.

Claim 21

In a data processing system including a plurality of processing elements interconnected with each other and with at least one memory element by an interconnection means, each of said processing elements selectively executing program tasks, said at least one memory element including multiple memory locations identifiable by corresponding memory addresses for storing data, apparatus for synchronizing operation of said plurality of processing elements, comprising: means for designating a selected memory location of a selected memory element to contain semaphore data; means for altering, by selected ones of said plurality of processing elements, said semaphore data whereby to indicate a status of selected tasks; means for sending, from said at least one requesting processing element to said selected memory element via said interconnecting means, a directive including (1) the address of said selected memory location, (2) a comparison value, and (3) an identification of the requesting processing element sending said directive; means for reading in said selected memory element said semaphore data; means for comparing in said memory element said semaphore data with said comparison value; means for notifying said requesting processing element via said interconnection means if said semaphore data matches said comparison value; means for storing said directive in said selected memory element if said semaphore data does not match said comparison value; means for monitoring in said memory element the altering of said semaphore data; and means for activating said reading, comparing, and notifying means when said semaphore data is altered.

Claim 22

In a data processing system including a plurality of processing elements interconnected with each other and with at least one memory element by an interconnection means, each of said processing elements selectively executing program tasks, said at least one memory element including multiple memory locations identifiable by corresponding memory addresses for storing data, apparatus for synchronizing operation of said plurality of processing elements, comprising: means for designating a selected memory location of a selected memory element to contain semaphore data; means for altering, by selected ones of said plurality of processing elements, said semaphore data whereby to indicate a status of selected tasks; means for sending, from said at least one requesting processing element to said selected memory element via said interconnecting means, a directive including (1) the address of said selected memory location, (2) a comparison value, and (3) an identification of the requesting processing element sending said directive; means for reading in said selected memory element said semaphore data; means for comparing in said memory element said semaphore data with said comparison value; means for notifying said requesting processing element via said interconnection means if said semaphore data matches said comparison value; means for storing said directive in said selected memory element if said semaphore data does not match said comparison value; means for monitoring in said memory element the altering of said semaphore data; and means for activating said reading, comparing, and notifying means when said semaphore data is altered.

Claim 23

Apparatus in accordance with claim 18 and further including means for returning the first read semaphore data to said requesting processing element regardless of whether the first read semaphore data matches said comparison value.

Claim 24

Apparatus in accordance with claim 18 wherein said directive includes a timeout value; and further including means for terminating said activating means when said timeout value is exceeded.

Claim 25

Apparatus in accordance with claim 18 wherein said means for notifying said requesting processing element includes means for sending said semaphore data to said requesting processing element.

Claim 26

Apparatus in accordance with claim 18 and further including means for assembling said directive in said requesting processing element.

Claim 27

Apparatus in accordance with claim 18 wherein said storing means includes means for storing said directive associatively with the address of said selected memory location.

Claim 28

Apparatus in accordance with claim 18 wherein said directive includes an identification of a requesting task performed by said requesting processing element.