Method of fabricating a bi-CMOS device

Claim 1

A method of fabricating simultaneously a polysilicon emitter bipolar transistor and a complementary pair of an n-channel and a p-channel field effect transistors in a common silicon semiconductor substrate, said bipolar transistor and n-channel field effect transistor being disposed in respective n-type wells in said substrate and said p-channel transistor being disposed in a substrate region located immediately between said n-type wells, the method consisting of the steps of; (a) providing a uniform single crystal silicon substrate of p-type material; (b) forming first and second spaced wells on n-type material in a major surface of the substrate by means of a first mask; (c) providing a silicon nitride film on said surface and patterning said film by means of a second mask to define device areas in register with said n-type wells for the bipolar and n-channel field effect transistor and over an undoped substrate region between said wells for the p-channel field effect transistor; (d) oxidising the substrate surface to form field oxide in those areas not protected by the nitride film; (e) removing the nitride film from said protected areas and providing a thin oxide film in those areas; (f) ion implanting a p-type layer beneath a said thin oxide film into said first n-type well by means of a third mask whereby to provide a base region for the bipolar transistor; (g) providing by means of a fourth mask a window in that thin oxide film below which the p-type layer is implanted; (h) depositing a layer of polycrystalline silicon (polysilicon) on said oxidised major surface and patterning said polysilicon layer by means of a fifth mask to define simultaneously a polysilicon emitter body in register with the window over the p-type layer in said first well, a first gate electrode over the second n-type well, and a second gate electrode over the substrate region between the well, said gate electrode being disposed each on or over the thin oxide; (i) ion implanting a p-type dopant to provide p + -type base contact regions contiguous with the p-type layer in said first well to form the base structure of the bipolar transistor, p + -type drain and source regions for the n-channel transistor in said second n-type well and a p + -type substrate contact region between the wells, the polysilicon emitter body and the first polysilicon gate providing alignment masks for the p-type base contact and source and drain regions respectively, and a sixth mask providing, in combination with the patterned field oxide, for the positioning of the p + -type substrate contact; (j) ion implanting by means of a seventh mask an n + -type dopant to provide an n + -type collector contact region in said first well and spaced from the base structure, n + -type drain and source regions for the p-channel transistor in the substrate region between the wells, and an n + -type well contact in said seventh well; (k) oxidising the substrate surface, applying a glass layer thereto, and patterning said glass layer by means of an eighth mask to provide contact windows in the glass layer exposing the p + -type base contact regions and the collector contact region of the bipolar transistor, the drain and source regions of the p-channel and n-channel transistors, and the well contact, the oxidising step providing thermal drive-in of the ion implants; (l) metallizing the substrate surface and patterning the metallization by means of a ninth mask to contact the exposed regions via said contact windows.

Claim 2

A method of fabricating simultaneously a polysilicon emitter bipolar transistor and a complementary pair of an n-channel and a p-channel field effect transistors in a common silicon semiconductor substrate, said bipolar transistor and n-channel field effect transistor being disposed in respective n-type wells in said substrate and said p-channel transistor being disposed in a substrate region located immediately between said n-type wells, the method consisting of the steps of; (a) providing a uniform single crystal silicon substrate of p-type material; (b) forming first and second spaced wells on n-type material in a major surface of the substrate by means of a first mask; (c) providing a silicon nitride film on said surface and patterning said film by means of a second mask to define device areas in register with said n-type wells for the bipolar and n-channel field effect transistor and over an undoped substrate region between said wells for the p-channel field effect transistor; (d) oxidising the substrate surface to form field oxide in those areas not protected by the nitride film; (e) removing the nitride film from said protected areas and providing a thin oxide film in those areas; (f) ion implanting a p-type layer beneath a said thin oxide film into said first n-type well by means of a third mask whereby to provide a base region for the bipolar transistor; (g) providing by means of a fourth mask a window in that thin oxide film below which the p-type layer is implanted; (h) depositing a layer of polycrystalline silicon (polysilicon) on said oxidised major surface and patterning said polysilicon layer by means of a fifth mask to define simultaneously a polysilicon emitter body in register with the window over the p-type layer in said first well, a first gate electrode over the second n-type well, and a second gate electrode over the substrate region between the well, said gate electrode being disposed each on or over the thin oxide; (i) ion implanting a p-type dopant to provide p + -type base contact regions contiguous with the p-type layer in said first well to form the base structure of the bipolar transistor, p + -type drain and source regions for the n-channel transistor in said second n-type well and a p + -type substrate contact region between the wells, the polysilicon emitter body and the first polysilicon gate providing alignment masks for the p-type base contact and source and drain regions respectively, and a sixth mask providing, in combination with the patterned field oxide, for the positioning of the p + -type substrate contact; (j) ion implanting by means of a seventh mask an n + -type dopant to provide an n + -type collector contact region in said first well and spaced from the base structure, n + -type drain and source regions for the p-channel transistor in the substrate region between the wells, and an n + -type well contact in said seventh well; (k) oxidising the substrate surface, applying a glass layer thereto, and patterning said glass layer by means of an eighth mask to provide contact windows in the glass layer exposing the p + -type base contact regions and the collector contact region of the bipolar transistor, the drain and source regions of the p-channel and n-channel transistors, and the well contact, the oxidising step providing thermal drive-in of the ion implants; (l) metallizing the substrate surface and patterning the metallization by means of a ninth mask to contact the exposed regions via said contact windows.