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US4964142A Expired / Lapsed US ⏱️ 0.0 years remaining

Receiver synchronization in encoder/decoder

Assignee: GlobalFoundries Inc
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Filing: 1987-07-15
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Granted: 1990-10-16
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Expires: 2007-07-15
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Abstract

Abstract Method and apparatus suited for use with a decoder receiving data serially from a network is disclosed providing synchronization throughout reception and decoding of packets of symbols. An appropriately-delayed read pointer initialization strobe used by an elastic buffer portion of the receiver provides the sequence of synchronization signals which avoids deletion of bits of packet preamble.

Inventors

  • 👤 Kadiresan Annamalai

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 16:43
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0632

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 271 words
A method of synchronizing the decoding of packets of symbols stored in a n-bit register, said symbols serially received from a network and serially stored in an elastic buffer, said elastic buffer being responsive to a buffer reset signal and including a read pointer means, coupled to said elastic buffer, for determining a buffer read location of signals to be serially read from said elastic buffer, said elastic buffer, responsive to said buffer reset signal, providing a read pointer initialization signal to said read pointer means to initialize said read pointer means in response to said buffer reset signal, said elastic buffer and said read pointer means being responsive to a source of clock signals having a predetermined period, said method comprising the steps of: (a) generating a signal from said read pointer initialization signal; (b) delaying said generating signal for a predetermined time period; (c) generating a synchronization signal during a clock period; (d) detecting a predetermined start-of-packet delimiter upon serial reception of signals from said elastic buffer, delayed by a first predetermined number of said clock periods m, said packet delimiter comprising signals received over a second predetermined number of said clock periods n; (e) generating said synchronization signal during the next clock period following said detection at step (d) and at every second predetermined number of clock periods thereafter; (f) loading into said n-bit register, in parallel, synchronized by said signal generated at step (e), signals, representing said symbols, serially read from said elastic buffer, delayed by said m clock periods, during the second predetermined number of clock periods preceding generation of said signal generated by step (e).
Claim 2
Independent Claim 271 words
A method of synchronizing the decoding of packets of symbols stored in a n-bit register, said symbols serially received from a network and serially stored in an elastic buffer, said elastic buffer being responsive to a buffer reset signal and including a read pointer means, coupled to said elastic buffer, for determining a buffer read location of signals to be serially read from said elastic buffer, said elastic buffer, responsive to said buffer reset signal, providing a read pointer initialization signal to said read pointer means to initialize said read pointer means in response to said buffer reset signal, said elastic buffer and said read pointer means being responsive to a source of clock signals having a predetermined period, said method comprising the steps of: (a) generating a signal from said read pointer initialization signal; (b) delaying said generating signal for a predetermined time period; (c) generating a synchronization signal during a clock period; (d) detecting a predetermined start-of-packet delimiter upon serial reception of signals from said elastic buffer, delayed by a first predetermined number of said clock periods m, said packet delimiter comprising signals received over a second predetermined number of said clock periods n; (e) generating said synchronization signal during the next clock period following said detection at step (d) and at every second predetermined number of clock periods thereafter; (f) loading into said n-bit register, in parallel, synchronized by said signal generated at step (e), signals, representing said symbols, serially read from said elastic buffer, delayed by said m clock periods, during the second predetermined number of clock periods preceding generation of said signal generated by step (e).
Claim 3
Dependent Claim 58 words
A decoding synchronization method according to claim 1 wherein said symbols serially received from said network are serially loaded into an n-stage serial-to-parallel shift register responsive to said clock signals, and wherein step (e) further includes loading in parallel the contents of said serial-to-parallel shift register into said n-bit register, synchronized by said signal generated at step (e).
Claim 4
Dependent Claim 25 words
A decoding synchronization method according to claim 1 wherein said signal generated at step (b) is delayed one of said clock periods and wherein m=2.
Claim 5
Dependent Claim 62 words
A decoding synchronization apparatus according to claim 1 wherein said symbols serially received from said network are serially loaded into an n-stage serial-to-parallel shift register responsive to said clock signals, and synchronization signal generatng means further includes loading in parallel the contents of said serial-to-parllel shift register into said n-bit register, synchronized by said signal generated by said synchronization signal generating means.
Claim 6
Dependent Claim 26 words
A decoding synchronization apparatus according to claim 1 wherein said signal generated by said delaying means is delayed one of said clock periods and wherein m=2.
Claim 7
Independent Claim 279 words
An apparatus for synchronizing the decoding of packets of symbols stored in a n-bit register, said symbols serially received from a network and serially stored in an elastic buffer, said elastic buffer being responsive to a buffer reset signal and including a read pointer means, coupled to said elastic buffer, for determining a buffer read location of signals to be serially read from said elastic buffer, said elastic buffer, responsive to said buffer reset signal providing a read pointer initialization signal to said read pointer means to initialize said read pointer means in response to said buffer reset signal, said elastic buffer and said read pointer means responsive to a source of clock signals having a predetermined period, said apparatus comprising: means for generating a signal from said read pointer initialization signal; means for delaying said generating signal for a predetermined time period; means for generating a synchronization signal during a clock period; means for detecting a predetermined start-of-packet delimiter upon serial reception of signals from said elastic buffer, delayed by a first predetermined number of said clock periods m, said packet delimiter comprising signals received over a second predetermined number of said clock periods n, said synchronization signal generating means generating a signal during the next clock period following said detection by said detecting means and at every second predetermined number of clock periods thereafter; and means for loading into said n-bit register, in parallel, synchronized by said signal generated by said signals representing said symbols serially read from said elastic buffer, delayed by said m clock periods, during the second predetermined number of clock periods preceding operation of said signal generated by said synchronization signal generating means.
Claim 8
Independent Claim 279 words
An apparatus for synchronizing the decoding of packets of symbols stored in a n-bit register, said symbols serially received from a network and serially stored in an elastic buffer, said elastic buffer being responsive to a buffer reset signal and including a read pointer means, coupled to said elastic buffer, for determining a buffer read location of signals to be serially read from said elastic buffer, said elastic buffer, responsive to said buffer reset signal providing a read pointer initialization signal to said read pointer means to initialize said read pointer means in response to said buffer reset signal, said elastic buffer and said read pointer means responsive to a source of clock signals having a predetermined period, said apparatus comprising: means for generating a signal from said read pointer initialization signal; means for delaying said generating signal for a predetermined time period; means for generating a synchronization signal during a clock period; means for detecting a predetermined start-of-packet delimiter upon serial reception of signals from said elastic buffer, delayed by a first predetermined number of said clock periods m, said packet delimiter comprising signals received over a second predetermined number of said clock periods n, said synchronization signal generating means generating a signal during the next clock period following said detection by said detecting means and at every second predetermined number of clock periods thereafter; and means for loading into said n-bit register, in parallel, synchronized by said signal generated by said signals representing said symbols serially read from said elastic buffer, delayed by said m clock periods, during the second predetermined number of clock periods preceding operation of said signal generated by said synchronization signal generating means.

References Cited (Backward Citations)

US4573172A Cited
US4740962A Cited
US4748623A Cited
US4792966A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-10-15 1994-04-16 1994-10-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-10-15 1998-04-16 1998-10-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-10-15 2002-04-16 2002-10-16 $7700.00 Window Closed / Lapsed

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