Synchronizer for time division multiplexed data

Claim 2

A synchronizer for time division multiplexed data, said synchronizer comprising: a FIFO memory having an input configured to receive an incoming data stream occurring at a predetermined data rate and having an output configured to supply an output data stream at a data rate substantially equal to the predetermined data rate of the incoming stream; a register having an input coupled to the output of said FIFO memory, said register being for saving a predetermined series of bits from the output data stream, and said register having an output; means, having an input coupled to said register output, for comparing the series of bits in said register with a predetermined synchronization pattern, said comparing means having an output for providing a comparison output; and means, coupled to said comparing means output and said FIFO memory input, for adding a dummy bit to the incoming data stream when said comparison output indicates that the synchronization pattern did not occur.

Claim 3

A synchronizer as claimed in claim 1 additionally comprising means, coupled to said adding means, for initializing said FIFO memory when said comparing means indicates that the synchronization pattern did not occur within a predetermined amount of time.

Claim 4

A synchronizer as claimed in claim 1 wherein: the incoming data stream includes an incoming clock derived from the received data stream; said FIFO memory has a clock input adapted to receive the incoming clock; and said adding means comprises an astable multivibrator having an input trigger adapted to receive the incoming clock and having an output coupled to the clock input of said FIFO memory.

Claim 5

A synchronizer as claimed in claim 1 wherein said comparing means is configured to compare the series of bits in said register with the predetermined synchronization pattern only once for a first predetermined number of bits of data from the output data stream.

Claim 6

A synchronizer as claimed in claim 4 wherein said adding means is configured to add the dummy bit to the incoming data stream only once for a second predetermined number of bits of data from the output data stream, said second predetermined number being greater than the first predetermined number, and said addition occurring when said comparing means indicates that the series of bits in said register does not match the synchronization pattern.

Claim 7

A synchronizer as claimed in claim 4 wherein: said synchronizer operates in an acquisition mode where said synchronizer has not achieved synchronization with the incoming data stream and in a maintenance mode where said synchronizer has achieved synchronization with the incoming data stream; and said comparing means is configured to compare the series of bits in said register with the predetermined synchronization pattern only once for a second predetermined number of bits of data from the output data stream during the maintenance mode, said second predetermined number being greater than the first predetermined number.

Claim 8

A synchronizer as claimed in claim 1 wherein: the incoming data stream includes an incoming clock derived from the incoming data stream, the incoming clock causing bits of data to be loaded into said FIFO memory; and wherein said synchronizer additionally comprises a clock generator which is isolated from the incoming clock, couples to said FIFO memory, and provides a clock signal which removes data from said FIFO memory.

Claim 11

A method as claimed in claim 8 additionally comprising the step of repeating said saving, testing, and adding steps until said testing step indicates the occurrence of the synchronization pattern.

Claim 12

A method as claimed in claim 8 additionally comprising the step of initializing the FIFO memory when said testing step fails to indicate the occurrence of the synchronization pattern within a predetermined amount of time.

Claim 13

A method claimed in claim 8 additionally comprising the step of permitting operation of said testing step only once for a predetermined number of bits of the output data stream.

Claim 14

A method as claimed in claim 11 additionally comprising the step of permitting operation of said adding step only once in a predetermined number of occurrences of said testing step.

Claim 15

A method as claimed in claim 8 wherein: said routing step includes the step of utilizing an incoming clock derived from the incoming data stream to route the incoming data stream into the FIFO memory; and said retrieving step includes the step of isolating a local clock exhibiting substantially the same rate as the incoming clock from the incoming clock.

Claim 16

A method as claimed in claim 13 wherein said adding step includes the step of referencing to the incoming clock a point in time at which the bit is added to the incoming data stream.

Claim 17

A method as claimed in claim 8 additionally comprising the steps of: discriminating between an acquisition mode where synchronization has not been achieved and a maintenance mode where synchronization has been achieved; and permitting operation of said testing step only once in a first predetermined number of bits of data from the output data stream in the acquisition mode.

Claim 18

A method as claimed in claim 15 additionally coaprising the step of permitting operation of said testing step only once in a second predetermined number of bits of data from the output data stream in the maintenance mode, the second predetermined number being greater than the first predetermined number.

Claim 19

A method as claimed in claim 15 additionally comprising the step of permitting continuation of the maintenance mode when said testing step provides a single indication that the synchronization pattern did not occur.

Claim 20

A synchronizer for time division multiplexed data, said synchronizer comprising: a FIFO memory having an input configured to receive an incoming data stream occurring at a predetermined data rate and having an output configured to supply an output data stress at a data rate substantially equal to the predetermined data rate of the incoming data stream; a shift register having an input coupled to the output of said FIFO memory, said shift register being for saving a predetermined series of bits from the output data stream, and said shift register having an output; a comparator having an input coupled to said shift register output and having an output, said comparator being for comparing the series of bits in said shift register with a predetermined synchronization pattern; a latch having an input coupled to the output of said comparator and having an output, said latch being for sampling a signal generated by said comparator only once for a first predetermined number of bits of data from the output data stream; and means, having an input coupled to the output of said latch and having an output coupled to said FIFO memory input, for adding a dummy bit to the incoming data stream only once in a second predeteremined number of bits of data from the output data stream, said second predetermined number being greater than the first predetermined number, when the sampled output from said latch indicates that the series of bits saved in said shift register did not match the predetermined synchronization pattern.

Claim 21

A synchronizer for time division multiplexed data, said synchronizer comprising: a FIFO memory having an input configured to receive an incoming data stream occurring at a predetermined data rate and having an output configured to supply an output data stress at a data rate substantially equal to the predetermined data rate of the incoming data stream; a shift register having an input coupled to the output of said FIFO memory, said shift register being for saving a predetermined series of bits from the output data stream, and said shift register having an output; a comparator having an input coupled to said shift register output and having an output, said comparator being for comparing the series of bits in said shift register with a predetermined synchronization pattern; a latch having an input coupled to the output of said comparator and having an output, said latch being for sampling a signal generated by said comparator only once for a first predetermined number of bits of data from the output data stream; and means, having an input coupled to the output of said latch and having an output coupled to said FIFO memory input, for adding a dummy bit to the incoming data stream only once in a second predeteremined number of bits of data from the output data stream, said second predetermined number being greater than the first predetermined number, when the sampled output from said latch indicates that the series of bits saved in said shift register did not match the predetermined synchronization pattern.