Programmable circuit for series-parallel transformation of a digital signal

Claim 1

a circuit for the series-parallel transformation of a series digital signal having sequences of synchronization words determining a frame thereof into a sequence of parallel binary words comprising: an input shift register controlled by a series clock said shift register being connected to a storage register controlled by a parallel clock, a coincidence detector circuit having a first input which receives a reference synchronization word, a second input receiving the series digital signal from an output of said shift register and an output delivering coincidence pulses when the reference word is detected in the series digital signal, a phase comparator receiving, on a first input thereof the coincidence pulses and, on a second input thereof, a phase reference signal, at a timing rate of the parallel words, a divider whose divisor is programmable to a value related to the number of parallel word bits, controlled by said series clock for supplying said phase reference signal, said phase comparator delivering pulses I or I at two outputs thereof depending on whether the coincidence pulses are in phase or out of phase with the phase reference signal, and a logic hysteresis circuit connected to the outputs of said phase comparator and having two outputs upon which are supplied respective validated pulses Ival or Ival when a predetermined number of successive pulses I or I respectively, are detected, the validated pulses being applied to a sync control input of the programmable divider.