Patent US4964117A successfully refreshed from Google Patents.
US4964117A
Expired / Lapsed
US
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Timing synchronizing circuit for baseband data signals
Assignee: Vermont Technical College
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Filing: 1988-10-04
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Granted: 1990-10-16
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Expires: 2008-10-04
Abstract
Abstract A timing synchronizing circuit with a phase locked loop. A multiplexor is employed to cause the phase locked loop to alternate between a self-excited mode for maintaining the frequency of a recovered timing signal and a mode in which state transitions of a baseband data signal are compared with the phase locked loop feedback signal to adjust the frequency of the recovered timing signal.
Inventors
- 👤 John S. Shier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 04:35
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0079; H04L7/0083
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
191 words
A timing synchronizing circuit for recovering a clock from a data signal characterized by state transitions, the circuit comprising: a phase detector with first and second input terminals; a voltage controlled oscillator for generating a recovered clock signal; filter means for coupling the output of the phase detector to the voltage controlled oscillator; means for generating a feedback signal related to the recovered clock signal; means for coupling the feedback signal to the first input terminal of the phase detector; a data input terminal; state transition detection means coupled to the data input terminal and responsive to the recovered clock signal for generating a signal indicating the occurrence of state transitions of the data signal; means coupled to the data input terminal for generating a transition timing signal; and multiplexing means responsive to the state transition detection means for coupling the feedback signal to the second input terminal of the phase detector in the absence of state transitions of the data signal and for coupling the signal indicating occurrence of state transitions to the second input terminal of the phase detector when state transitions in the data signal have been detected.
Claim 2
Dependent Claim
191 words
A timing synchronizing circuit for recovering a clock from a data signal characterized by state transitions, the circuit comprising: a phase detector with first and second input terminals; a voltage controlled oscillator for generating a recovered clock signal; filter means for coupling the output of the phase detector to the voltage controlled oscillator; means for generating a feedback signal related to the recovered clock signal; means for coupling the feedback signal to the first input terminal of the phase detector; a data input terminal; state transition detection means coupled to the data input terminal and responsive to the recovered clock signal for generating a signal indicating the occurrence of state transitions of the data signal; means coupled to the data input terminal for generating a transition timing signal; and multiplexing means responsive to the state transition detection means for coupling the feedback signal to the second input terminal of the phase detector in the absence of state transitions of the data signal and for coupling the signal indicating occurrence of state transitions to the second input terminal of the phase detector when state transitions in the data signal have been detected.
Claim 3
Dependent Claim
77 words
The timing synchronizing circuit of claim 1 wherein the state transition detection means further includes: a first flip flop coupled to receive the data signal and clocked by the recovered clock signal; a second flip flop coupled to receive the output of the first flip flop and clocked by the recovered clock signal; and exclusive OR means for comparing the outputs of the first and second flip flops for generating a control signal for the multiplexing means.
Claim 4
Dependent Claim
38 words
The timing synchronizing circuit of claim 2 wherein the feedback signal generating means includes an edge triggered frequency dividing circuit producing a first signal with a frequency which is a harmonic of the frequency of the recovered clock.
Claim 5
Dependent Claim
42 words
The timing synchronizing circuit of claim 3 and further comprising inversion timing signal generating means including an edge triggered frequency dividing circuit for producing an inversion timing signal with a frequency which is a harmonic of the frequency of the recovered clock.
Claim 6
Dependent Claim
62 words
The timing synchronizing circuit of claim 4 wherein the edge triggered frequency dividing circuit of the feedback signal generating means and the edge triggered frequency dividing circuit of the inversion timing signal generating means are triggered on opposite edges of pulses of the recovered clock for providing signals of one-half the frequency of the recovered clock and having a fixed phase relationship.
Claim 7
Dependent Claim
86 words
The timing synchronizing circuit of claim 5 wherein the means for generating the transition timing signal includes a delay line connected in series with the data input terminal, a negating exclusive-OR circuit coupled to receive the output of the first flip flop and the timing signal, and an exclusive-OR circuit coupled to the output of the negating exclusive-OR circuit and to an output of the delay line for receiving the delayed data signal, with the output of the exclusive-OR circuit being connected to the multiplexing means.
Claim 8
Dependent Claim
19 words
The timing synchronizing circuit of claim 6 wherein the output of the first flip flop circuit is detected data.
Claim 9
Dependent Claim
172 words
A timing synchronizing circuit comprising: means for comparing the phases of two signals and generating a phase difference signal; reference signal generating means responsive to the phase difference signal for generating a reference signal; means for coupling the reference signal to the phase comparing means; means for detecting state transitions in a data signal and generating a control signal indicating the presence and absence of such transitions; means for generating a signal indicating timing of logic state transitions of the data signal; and multiplexing means responsive to the control signal for coupling the reference signal to the phase comparator means in the absence of state transitions of the data signal such that the phase comparator means compares the reference signal with itself, and for coupling the signal indicating timing of the logic state transitions in the data signal to the phase detector when a state transition in the data signal has occurred such that the phase comparator means compares the reference signal with the signal indicating the timing of logic state transitions.
Claim 10
Dependent Claim
172 words
A timing synchronizing circuit comprising: means for comparing the phases of two signals and generating a phase difference signal; reference signal generating means responsive to the phase difference signal for generating a reference signal; means for coupling the reference signal to the phase comparing means; means for detecting state transitions in a data signal and generating a control signal indicating the presence and absence of such transitions; means for generating a signal indicating timing of logic state transitions of the data signal; and multiplexing means responsive to the control signal for coupling the reference signal to the phase comparator means in the absence of state transitions of the data signal such that the phase comparator means compares the reference signal with itself, and for coupling the signal indicating timing of the logic state transitions in the data signal to the phase detector when a state transition in the data signal has occurred such that the phase comparator means compares the reference signal with the signal indicating the timing of logic state transitions.
Claim 11
Dependent Claim
92 words
The timing synchronizing circuit of claim 8 wherein the state transition detection means further includes: a first flip flop receiving a first signal related to the reference signal on a clock input terminal and the data signal on a data input terminal; a second flip flop receiving the first signal on a clock input terminal and the output of the first flip flop on a data input terminal; and control signal generating means responsive to the outputs of the first flip flop and the second flip flop for generating the control signal.
Claim 12
Dependent Claim
168 words
A timing synchronizing circuit comprising: a data input terminal for receiving a data signal; a clocked state transition detector connected to the data input terminal; a phase detector with first and second input terminals; a voltage controlled oscillator coupled to the phase detector for generating a recovered clock signal; means for coupling the recovered clock signal to the clocked state transition detector; means for generating a feedback signal related to the recovered clock signal and for applying the feedback signal to the first input terminal of the phase detector; means for generating a data signal state transition timing signal; and a multiplexer connected to the second input terminal of the phase detector and responsive to the transition detector for coupling the feedback signal to the second input terminal of the phase detector in the absence of state transitions of the data signal and for coupling state transitions of the data signal to the second terminal of the phase detector when state transitions in the data signal are present.
Claim 13
Dependent Claim
168 words
A timing synchronizing circuit comprising: a data input terminal for receiving a data signal; a clocked state transition detector connected to the data input terminal; a phase detector with first and second input terminals; a voltage controlled oscillator coupled to the phase detector for generating a recovered clock signal; means for coupling the recovered clock signal to the clocked state transition detector; means for generating a feedback signal related to the recovered clock signal and for applying the feedback signal to the first input terminal of the phase detector; means for generating a data signal state transition timing signal; and a multiplexer connected to the second input terminal of the phase detector and responsive to the transition detector for coupling the feedback signal to the second input terminal of the phase detector in the absence of state transitions of the data signal and for coupling state transitions of the data signal to the second terminal of the phase detector when state transitions in the data signal are present.
Claim 14
Independent Claim
164 words
A method of operating a phase lock loop used for recovery of a clock signal from a baseband data signal wherein the baseband data signal is subject to periods of relatively infrequent logic state transitions, and the phase lock loop includes a phase detector for comparing phase difference between two input signals, the method comprising the steps of: (a) establishing a recovered clock signal upon initial detection of logic state transitions, in a data signal; (b) self-exciting the phase lock loop in the absence of logic state transitions of the data signal by providing the recovered clock signal as both input signals to the phase detector; (c) detecting a logic state transition in the baseband data signal; (d) comparing the phase of the logic state transition with the phase of the recovered clock signal; (e) adjusting the frequency of the recovered clock signal to eliminate the phase difference between the recovered clock signal and the data signal transitions; and (f) returning to step (b).
Claim 15
Independent Claim
164 words
A method of operating a phase lock loop used for recovery of a clock signal from a baseband data signal wherein the baseband data signal is subject to periods of relatively infrequent logic state transitions, and the phase lock loop includes a phase detector for comparing phase difference between two input signals, the method comprising the steps of: (a) establishing a recovered clock signal upon initial detection of logic state transitions, in a data signal; (b) self-exciting the phase lock loop in the absence of logic state transitions of the data signal by providing the recovered clock signal as both input signals to the phase detector; (c) detecting a logic state transition in the baseband data signal; (d) comparing the phase of the logic state transition with the phase of the recovered clock signal; (e) adjusting the frequency of the recovered clock signal to eliminate the phase difference between the recovered clock signal and the data signal transitions; and (f) returning to step (b).
Claim 16
Dependent Claim
96 words
A timing synchronizing circuit comprising: a phase locked loop for generating a feedback signal; means for detecting state transitions in a data signal and generating a control signal indicating the presence and absence of the data transitions; means responsive to the data signal for generating a transition signal; multiplexing means responsive to the control signal for switching between the feedback signal and the transition signal as a function of the presence and absence of the data transitions in the data signal; and means for coupling the output of the multiplexing means to the phase locked loop.
Claim 17
Dependent Claim
96 words
A timing synchronizing circuit comprising: a phase locked loop for generating a feedback signal; means for detecting state transitions in a data signal and generating a control signal indicating the presence and absence of the data transitions; means responsive to the data signal for generating a transition signal; multiplexing means responsive to the control signal for switching between the feedback signal and the transition signal as a function of the presence and absence of the data transitions in the data signal; and means for coupling the output of the multiplexing means to the phase locked loop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-15 | 1994-04-16 | 1994-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-15 | 1998-04-16 | 1998-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-15 | 2002-04-16 | 2002-10-16 | $7700.00 | Window Closed / Lapsed |